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radeonsi: remove unused flags and user_flags params from clear/copy functions

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Remove the params from these:
- si_copy_buffer
- si_cp_dma_prepare
- si_cp_dma_clear_buffer
- si_cp_dma_realign_engine
- si_cp_dma_copy_buffer

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31193>
This commit is contained in:
Marek Olšák
2024-08-22 18:02:14 -04:00
committed by Marge Bot
parent 2f4a9e65a7
commit df6b5e3c05
10 changed files with 27 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeonsi/radeon_video.c
+2 -2
View File
@@ -113,13 +113,13 @@ bool si_vid_resize_buffer(struct pipe_context *context, struct radeon_cmdbuf *cs
uint64_t dst_offset = 0, src_offset = 0;
for (int i = 0; i < buf_ofst_info->num_units; i++) {
si_copy_buffer(sctx, &new_buf->res->b.b, &old_buf.res->b.b,
dst_offset, src_offset, buf_ofst_info->old_offset, 0);
dst_offset, src_offset, buf_ofst_info->old_offset);
dst_offset += buf_ofst_info->new_offset;
src_offset += buf_ofst_info->old_offset;
}
} else {
bytes = MIN2(new_buf->res->b.b.width0, old_buf.res->b.b.width0);
si_copy_buffer(sctx, &new_buf->res->b.b, &old_buf.res->b.b, 0, 0, bytes, 0);
si_copy_buffer(sctx, &new_buf->res->b.b, &old_buf.res->b.b, 0, 0, bytes);
}
context->flush(context, NULL, 0);
}
src/gallium/drivers/radeonsi/si_blit.c
+1 -1
View File
@@ -966,7 +966,7 @@ void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst
/* Handle buffers first. */
if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
si_barrier_before_simple_buffer_op(sctx, 0, dst, src);
si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
si_barrier_after_simple_buffer_op(sctx, 0, dst, src);
return;
}
src/gallium/drivers/radeonsi/si_buffer.c
+2 -2
View File
@@ -446,7 +446,7 @@ static void *si_buffer_transfer_map(struct pipe_context *ctx, struct pipe_resour
/* Copy the VRAM buffer to the staging buffer. */
si_barrier_before_simple_buffer_op(sctx, 0, &staging->b.b, resource);
si_copy_buffer(sctx, &staging->b.b, resource, box->x % SI_MAP_BUFFER_ALIGNMENT,
box->x, box->width, 0);
box->x, box->width);
si_barrier_after_simple_buffer_op(sctx, 0, &staging->b.b, resource);
data = si_buffer_map(sctx, staging, usage & ~PIPE_MAP_UNSYNCHRONIZED);
@@ -485,7 +485,7 @@ static void si_buffer_do_flush_region(struct pipe_context *ctx, struct pipe_tran
/* Copy the staging buffer into the original one. */
si_barrier_before_simple_buffer_op(sctx, 0, transfer->resource, &stransfer->staging->b.b);
si_copy_buffer(sctx, transfer->resource, &stransfer->staging->b.b, box->x, src_offset,
box->width, 0);
box->width);
si_barrier_after_simple_buffer_op(sctx, 0, transfer->resource, &stransfer->staging->b.b);
}
src/gallium/drivers/radeonsi/si_compute_blit.c
+4 -4
View File
@@ -389,7 +389,7 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
if (aligned_size) {
assert(clear_value_size == 4);
assert(!(flags & SI_OP_CS_RENDER_COND_ENABLE));
si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, offset, aligned_size, *clear_value, flags);
si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, offset, aligned_size, *clear_value);
}
offset += aligned_size;
@@ -425,16 +425,16 @@ static void si_pipe_clear_buffer(struct pipe_context *ctx, struct pipe_resource
}
void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
uint64_t dst_offset, uint64_t src_offset, unsigned size, unsigned flags)
uint64_t dst_offset, uint64_t src_offset, unsigned size)
{
if (!size)
return;
if (si_compute_clear_copy_buffer(sctx, dst, dst_offset, src, src_offset, size, NULL, 0, flags,
if (si_compute_clear_copy_buffer(sctx, dst, dst_offset, src, src_offset, size, NULL, 0, 0,
0, true))
return;
si_cp_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset, size, flags);
si_cp_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset, size);
}
void si_compute_shorten_ubyte_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
src/gallium/drivers/radeonsi/si_cp_dma.c
+9 -13
View File
@@ -110,8 +110,7 @@ void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs)
static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
struct pipe_resource *src, unsigned byte_count,
uint64_t remaining_size, unsigned user_flags,
bool *is_first, unsigned *packet_flags)
uint64_t remaining_size, bool *is_first, unsigned *packet_flags)
{
si_need_gfx_cs_space(sctx, 0);
@@ -142,7 +141,7 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
struct pipe_resource *dst, uint64_t offset, uint64_t size,
unsigned value, unsigned user_flags)
unsigned value)
{
struct si_resource *sdst = si_resource(dst);
uint64_t va = sdst->gpu_address + offset;
@@ -176,7 +175,7 @@ void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
if (!byte_count)
continue;
si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, user_flags, &is_first, &dma_flags);
si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, &is_first, &dma_flags);
/* Emit the clear packet. */
si_emit_cp_dma(sctx, cs, va, value, byte_count, dma_flags);
@@ -194,8 +193,7 @@ void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
*
* \param size Remaining size to the CP DMA alignment.
*/
static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size, unsigned user_flags,
bool *is_first)
static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size, bool *is_first)
{
uint64_t va;
unsigned dma_flags = 0;
@@ -219,7 +217,7 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size, uns
}
si_cp_dma_prepare(sctx, &sctx->scratch_buffer->b.b, &sctx->scratch_buffer->b.b, size, size,
user_flags, is_first, &dma_flags);
is_first, &dma_flags);
va = sctx->scratch_buffer->gpu_address;
si_emit_cp_dma(sctx, &sctx->gfx_cs, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags);
@@ -227,12 +225,10 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size, uns
/**
* Do memcpy between buffers using CP DMA.
*
* \param user_flags bitmask of SI_CPDMA_*
*/
void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
unsigned size, unsigned user_flags)
unsigned size)
{
assert(size);
assert(dst && src);
@@ -315,7 +311,7 @@ void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
if (!byte_count)
continue;
si_cp_dma_prepare(sctx, dst, src, byte_count, size + skipped_size + realign_size, user_flags,
si_cp_dma_prepare(sctx, dst, src, byte_count, size + skipped_size + realign_size,
&is_first, &dma_flags);
si_emit_cp_dma(sctx, &sctx->gfx_cs, main_dst_offset, main_src_offset, byte_count, dma_flags);
@@ -329,7 +325,7 @@ void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
if (skipped_size) {
unsigned dma_flags = 0;
si_cp_dma_prepare(sctx, dst, src, skipped_size, skipped_size + realign_size, user_flags,
si_cp_dma_prepare(sctx, dst, src, skipped_size, skipped_size + realign_size,
&is_first, &dma_flags);
si_emit_cp_dma(sctx, &sctx->gfx_cs, dst_offset, src_offset, skipped_size, dma_flags);
@@ -337,7 +333,7 @@ void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
/* Finally, realign the engine if the size wasn't aligned. */
if (realign_size)
si_cp_dma_realign_engine(sctx, realign_size, user_flags, &is_first);
si_cp_dma_realign_engine(sctx, realign_size, &is_first);
sctx->num_cp_dma_calls++;
}
src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
+1 -1
View File
@@ -58,7 +58,7 @@ void si_init_cp_reg_shadowing(struct si_context *sctx)
if (sctx->shadowing.registers) {
/* We need to clear the shadowed reg buffer. */
si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, &sctx->shadowing.registers->b.b,
0, sctx->shadowing.registers->bo_size, 0, 0);
0, sctx->shadowing.registers->bo_size, 0);
si_barrier_after_simple_buffer_op(sctx, 0, &sctx->shadowing.registers->b.b, NULL);
/* Create the shadowing preamble. (allocate enough dwords because the preamble is large) */
src/gallium/drivers/radeonsi/si_pipe.c
+1 -1
View File
@@ -1088,7 +1088,7 @@ static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags)
si_resource(buf)->gpu_address = 0; /* cause a VM fault */
if (test_flags & DBG(TEST_VMFAULT_CP)) {
si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4);
ctx->flush(ctx, NULL, 0);
puts("VM fault test: CP - done.");
}
src/gallium/drivers/radeonsi/si_pipe.h
+3 -3
View File
@@ -1499,7 +1499,7 @@ void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *
unsigned dst_offset, unsigned size, uint32_t clear_value,
uint32_t writebitmask, unsigned flags);
void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
uint64_t dst_offset, uint64_t src_offset, unsigned size, unsigned flags);
uint64_t dst_offset, uint64_t src_offset, unsigned size);
void si_compute_shorten_ubyte_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
uint64_t dst_offset, uint64_t src_offset, unsigned size, unsigned flags);
void si_compute_clear_image_dcc_single(struct si_context *sctx, struct si_texture *tex,
@@ -1526,10 +1526,10 @@ void si_init_compute_blit_functions(struct si_context *sctx);
void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs);
void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
struct pipe_resource *dst, uint64_t offset, uint64_t size,
unsigned value, unsigned user_flags);
unsigned value);
void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
unsigned size, unsigned user_flags);
unsigned size);
void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset,
unsigned size, unsigned dst_sel, unsigned engine, const void *data);
void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
src/gallium/drivers/radeonsi/si_shader.c
+1 -1
View File
@@ -986,7 +986,7 @@ static void post_upload_binary(struct si_screen *sscreen, struct si_shader *shad
* them available.
*/
si_cp_dma_copy_buffer(upload_ctx, &shader->bo->b.b, staging, 0, staging_offset,
binary_size, 0);
binary_size);
si_barrier_after_simple_buffer_op(upload_ctx, 0, &shader->bo->b.b, staging);
upload_ctx->flags |= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_L2;
src/gallium/drivers/radeonsi/si_test_dma_perf.c
+3 -3
View File
@@ -208,7 +208,7 @@ void si_test_dma_perf(struct si_screen *sscreen)
if (method == METHOD_DEFAULT) {
if (is_copy) {
si_barrier_before_simple_buffer_op(sctx, 0, dst, src);
si_copy_buffer(sctx, dst, src, dst_offset, src_offset, size, 0);
si_copy_buffer(sctx, dst, src, dst_offset, src_offset, size);
si_barrier_after_simple_buffer_op(sctx, 0, dst, src);
} else {
sctx->b.clear_buffer(&sctx->b, dst, dst_offset, size, &clear_value,
@@ -230,7 +230,7 @@ void si_test_dma_perf(struct si_screen *sscreen)
}
si_barrier_before_simple_buffer_op(sctx, 0, dst, src);
si_cp_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset, size, 0);
si_cp_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset, size);
si_barrier_after_simple_buffer_op(sctx, 0, dst, src);
} else {
/* CP DMA clears must be aligned to 4 bytes. */
@@ -244,7 +244,7 @@ void si_test_dma_perf(struct si_screen *sscreen)
assert(clear_value_size == 4);
si_barrier_before_simple_buffer_op(sctx, 0, dst, src);
si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, dst_offset, size,
clear_value[0], 0);
clear_value[0]);
si_barrier_after_simple_buffer_op(sctx, 0, dst, src);
}
} else {