radv/aco: lower IO for all stages outside of ACO

Lowering IO for VS, TCS, TES and GS still have to be done for LLVM.

No fossils-db change on NAVI10.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6897>

src/amd/compiler/aco_instruction_selection_setup.cpp

@@ -375,13 +375,6 @@ RegClass get_reg_class(isel_context *ctx, RegType type, unsigned components, uns
       return RegClass::get(type, components * bitsize / 8u);
 }
 
-int
-type_size(const struct glsl_type *type, bool bindless)
-{
-   // TODO: don't we need type->std430_base_alignment() here?
-   return glsl_count_attribute_slots(type, false);
-}
-
 bool
 mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
                        unsigned bit_size,
@@ -653,9 +646,6 @@ setup_nir(isel_context *ctx, nir_shader *nir)
       lower_to_scalar = true;
       lower_pack = true;
    }
-   if (nir->info.stage != MESA_SHADER_COMPUTE &&
-       nir->info.stage != MESA_SHADER_FRAGMENT)
-      nir_lower_io(nir, nir_var_shader_in | nir_var_shader_out, type_size, (nir_lower_io_options)0);
 
    lower_to_scalar |= nir_opt_shrink_vectors(nir);
 

src/amd/vulkan/radv_pipeline.c

@@ -2973,12 +2973,11 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
 				           nir_lower_non_uniform_image_access);
 			}
 			NIR_PASS_V(nir[i], nir_lower_memory_model);
+
+			radv_lower_io(device, nir[i]);
 		}
 	}
 
-	if (nir[MESA_SHADER_FRAGMENT])
-		radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
-
 	for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
 		if (radv_can_dump_shader(device, modules[i], false))
 			nir_print_shader(nir[i], stderr);

src/amd/vulkan/radv_shader.c

@@ -755,11 +755,21 @@ lower_view_index(nir_shader *nir)
 }
 
 void
-radv_lower_fs_io(nir_shader *nir)
+radv_lower_io(struct radv_device *device, nir_shader *nir)
 {
-	NIR_PASS_V(nir, lower_view_index);
-	nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs,
-				    MESA_SHADER_FRAGMENT);
+	if (nir->info.stage == MESA_SHADER_COMPUTE)
+		return;
+
+	/* TODO: Lower IO for all stages with LLVM. */
+	if (nir->info.stage != MESA_SHADER_FRAGMENT &&
+	    radv_use_llvm_for_stage(device, nir->info.stage))
+		return;
+
+	if (nir->info.stage == MESA_SHADER_FRAGMENT) {
+		NIR_PASS_V(nir, lower_view_index);
+		nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs,
+					    MESA_SHADER_FRAGMENT);
+	}
 
 	NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out, type_size_vec4, 0);
 

src/amd/vulkan/radv_shader.h

@@ -634,6 +634,6 @@ get_tcs_num_patches(unsigned tcs_num_input_vertices,
 }
 
 void
-radv_lower_fs_io(nir_shader *nir);
+radv_lower_io(struct radv_device *device, nir_shader *nir);
 
 #endif