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intel/fs/xe2+: Update TASK/MESH payload setup for Xe2 reg size.

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Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
This commit is contained in:
Caio Oliveira
2022-09-11 01:01:17 -07:00
committed by Jordan Justen
parent 8944ac7d6c
commit dd632bf527
1 changed files with 6 additions and 6 deletions
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src/intel/compiler/brw_fs_thread_payload.cpp
+6 -6
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@@ -455,15 +455,15 @@ task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v)
*/
task_urb_input = brw_ud1_grf(0, 7);
}
r++;
r += reg_unit(v.devinfo);
local_index = brw_uw8_grf(1, 0);
r++;
if (v.dispatch_width == 32)
r++;
local_index = brw_uw8_grf(r, 0);
r += reg_unit(v.devinfo);
if (v.devinfo->ver < 20 && v.dispatch_width == 32)
r += reg_unit(v.devinfo);
inline_parameter = brw_ud1_grf(r, 0);
r++;
r += reg_unit(v.devinfo);
num_regs = r;
}