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st/glsl_to_nir: skip forced array splitting for tcs

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nir_lower_io_to_temporaries() does not support tcs so we cannot
assume there are no indirects here. Also the radeonsi backend
(the only backend to support tess) has support for tcs indirects
so there is no need to lower them anyway.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Timothy Arceri
2017-12-12 13:49:41 +11:00
parent acab52f520
commit dd119a4263
1 changed files with 2 additions and 1 deletions
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src/mesa/state_tracker/st_glsl_to_nir.cpp
+2 -1
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@@ -642,7 +642,8 @@ st_finalize_nir(struct st_context *st, struct gl_program *prog,
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies);
NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
if (nir->info.stage != MESA_SHADER_TESS_CTRL)
NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
if (nir->info.stage == MESA_SHADER_VERTEX) {
/* Needs special handling so drvloc matches the vbo state: */