anv/iris: add note about Wa_18039438632 for RT flush after SBA

Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31801>
2024-10-23 13:58:08 +03:00
parent c0bceaf057
commit dcb88ea4ab
2 changed files with 4 additions and 0 deletions
@@ -252,6 +252,8 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
    * necessary prior to changing the surface state base address.  Without
    * this, we get GPU hangs when using multi-level command buffers which
    * clear depth, reset state base address, and then go render stuff.
+    *
+    * Render target cache flush before SBA is required by Wa_18039438632.
    */
   genx_batch_emit_pipe_control(&cmd_buffer->batch, device->info,
                                cmd_buffer->state.current_pipeline,