From dcb88ea4ab1b6ddc2929647b162bbb00863601dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Wed, 23 Oct 2024 13:58:08 +0300 Subject: [PATCH] anv/iris: add note about Wa_18039438632 for RT flush after SBA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Part-of: --- src/gallium/drivers/iris/iris_state.c | 2 ++ src/intel/vulkan/genX_cmd_buffer.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index e92f8fa1a8f..72fc4cdea4f 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -428,6 +428,8 @@ flush_before_state_base_change(struct iris_batch *batch) * insufficient, we need to ensure that any rendering operations from * other processes are definitely complete before we try to do our own * rendering. It's a bit of a big hammer but it appears to work. + * + * Render target cache flush before SBA is required by Wa_18039438632. */ iris_emit_end_of_pipe_sync(batch, "change STATE_BASE_ADDRESS (flushes)", diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 410ccfc0573..22bdce7e9ec 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -252,6 +252,8 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) * necessary prior to changing the surface state base address. Without * this, we get GPU hangs when using multi-level command buffers which * clear depth, reset state base address, and then go render stuff. + * + * Render target cache flush before SBA is required by Wa_18039438632. */ genx_batch_emit_pipe_control(&cmd_buffer->batch, device->info, cmd_buffer->state.current_pipeline,