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i965: use align1 access mode for instructions with execSize=1 in VS

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All operands must be 16-bytes aligned in aligh16 mode. This fixes l_xxx.c
in oglconform.
This commit is contained in:
Xiang, Haihao
2010-12-24 09:34:50 +08:00
parent 8249321604
commit dc987adc9f
1 changed files with 2 additions and 0 deletions
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src/mesa/drivers/dri/i965/brw_eu_emit.c
+2
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@@ -1727,6 +1727,7 @@ void brw_dp_READ_4_vs(struct brw_compile *p,
/* Setup MRF[1] with location/offset into const buffer */
brw_push_insn_state(p);
brw_set_access_mode(p, BRW_ALIGN_1);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
@@ -1774,6 +1775,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
/* Setup MRF[1] with offset into const buffer */
brw_push_insn_state(p);
brw_set_access_mode(p, BRW_ALIGN_1);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);