radeonsi: use ac_surface_print_info in si_print_texture_info
Pieces of information not printed by ac_surface_print_info are still printed in si_print_texture_info. Signed-off-by: Simon Ser <contact@emersion.fr> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5734>
This commit is contained in:
Simon Ser
@@ -860,102 +860,40 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
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struct u_log_context *log)
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{
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int i;
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FILE *f;
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char *surf_info = NULL;
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size_t surf_info_size;
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/* Common parameters. */
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u_log_printf(log,
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" Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
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"blk_h=%u, array_size=%u, last_level=%u, "
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"bpe=%u, nsamples=%u, flags=0x%x, %s\n",
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tex->buffer.b.b.width0, tex->buffer.b.b.height0, tex->buffer.b.b.depth0,
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tex->surface.blk_w, tex->surface.blk_h, tex->buffer.b.b.array_size,
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tex->buffer.b.b.last_level, tex->surface.bpe, tex->buffer.b.b.nr_samples,
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tex->surface.flags, util_format_short_name(tex->buffer.b.b.format));
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" Info: npix_x=%u, npix_y=%u, npix_z=%u, "
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"array_size=%u, last_level=%u, nsamples=%u",
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tex->buffer.b.b.width0, tex->buffer.b.b.height0,
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tex->buffer.b.b.depth0, tex->buffer.b.b.array_size,
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tex->buffer.b.b.last_level, tex->buffer.b.b.nr_samples);
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if (tex->surface.htile_offset)
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u_log_printf(log, ", tc_compatible_htile=%u", tex->tc_compatible_htile);
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u_log_printf(log, ", %s\n",
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util_format_short_name(tex->buffer.b.b.format));
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f = open_memstream(&surf_info, &surf_info_size);
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if (!f)
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return;
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ac_surface_print_info(f, &sscreen->info, &tex->surface);
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fclose(f);
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u_log_printf(log, "%s", surf_info);
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free(surf_info);
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if (sscreen->info.chip_class >= GFX9) {
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u_log_printf(log,
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" Surf: size=%" PRIu64 ", slice_size=%" PRIu64 ", "
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"alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
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tex->surface.surf_size, tex->surface.u.gfx9.surf_slice_size,
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tex->surface.surf_alignment, tex->surface.u.gfx9.surf.swizzle_mode,
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tex->surface.u.gfx9.surf.epitch, tex->surface.u.gfx9.surf_pitch);
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if (tex->surface.fmask_offset) {
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u_log_printf(log,
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" FMASK: offset=%" PRIu64 ", size=%" PRIu64 ", "
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"alignment=%u, swmode=%u, epitch=%u\n",
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tex->surface.fmask_offset, tex->surface.fmask_size,
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tex->surface.fmask_alignment, tex->surface.u.gfx9.fmask.swizzle_mode,
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tex->surface.u.gfx9.fmask.epitch);
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}
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if (tex->cmask_buffer) {
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u_log_printf(log,
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" CMask: offset=%" PRIu64 ", size=%u, "
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"alignment=%u\n",
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tex->surface.cmask_offset, tex->surface.cmask_size,
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tex->surface.cmask_alignment);
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}
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if (tex->surface.htile_offset) {
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u_log_printf(log,
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" HTile: offset=%" PRIu64 ", size=%u, alignment=%u\n",
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tex->surface.htile_offset, tex->surface.htile_size,
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tex->surface.htile_alignment);
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}
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if (tex->surface.dcc_offset) {
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u_log_printf(log,
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" DCC: offset=%" PRIu64 ", size=%u, "
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"alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
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tex->surface.dcc_offset, tex->surface.dcc_size, tex->surface.dcc_alignment,
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tex->surface.u.gfx9.display_dcc_pitch_max, tex->surface.num_dcc_levels);
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}
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if (tex->surface.u.gfx9.stencil_offset) {
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u_log_printf(log, " Stencil: offset=%" PRIu64 ", swmode=%u, epitch=%u\n",
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tex->surface.u.gfx9.stencil_offset, tex->surface.u.gfx9.stencil.swizzle_mode,
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tex->surface.u.gfx9.stencil.epitch);
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}
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return;
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}
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u_log_printf(log,
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" Layout: size=%" PRIu64 ", alignment=%u, bankw=%u, "
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"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
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tex->surface.surf_size, tex->surface.surf_alignment, tex->surface.u.legacy.bankw,
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tex->surface.u.legacy.bankh, tex->surface.u.legacy.num_banks,
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tex->surface.u.legacy.mtilea, tex->surface.u.legacy.tile_split,
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tex->surface.u.legacy.pipe_config, (tex->surface.flags & RADEON_SURF_SCANOUT) != 0);
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if (tex->surface.fmask_offset)
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u_log_printf(
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log,
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" FMask: offset=%" PRIu64 ", size=%" PRIu64 ", alignment=%u, pitch_in_pixels=%u, "
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"bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
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tex->surface.fmask_offset, tex->surface.fmask_size, tex->surface.fmask_alignment,
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tex->surface.u.legacy.fmask.pitch_in_pixels, tex->surface.u.legacy.fmask.bankh,
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tex->surface.u.legacy.fmask.slice_tile_max, tex->surface.u.legacy.fmask.tiling_index);
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if (tex->cmask_buffer)
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u_log_printf(log,
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" CMask: offset=%" PRIu64 ", size=%u, alignment=%u, "
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"slice_tile_max=%u\n",
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tex->surface.cmask_offset, tex->surface.cmask_size, tex->surface.cmask_alignment,
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tex->surface.u.legacy.cmask_slice_tile_max);
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if (tex->surface.htile_offset)
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u_log_printf(log,
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" HTile: offset=%" PRIu64 ", size=%u, "
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"alignment=%u, TC_compatible = %u\n",
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tex->surface.htile_offset, tex->surface.htile_size, tex->surface.htile_alignment,
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tex->tc_compatible_htile);
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if (tex->surface.dcc_offset) {
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u_log_printf(log, " DCC: offset=%" PRIu64 ", size=%u, alignment=%u\n",
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tex->surface.dcc_offset, tex->surface.dcc_size, tex->surface.dcc_alignment);
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for (i = 0; i <= tex->buffer.b.b.last_level; i++)
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u_log_printf(log,
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" DCCLevel[%i]: enabled=%u, offset=%u, "
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" DCCLevel[%i]: enabled=%u, offset=%u, "
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"fast_clear_size=%u\n",
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i, i < tex->surface.num_dcc_levels, tex->surface.u.legacy.level[i].dcc_offset,
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tex->surface.u.legacy.level[i].dcc_fast_clear_size);
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@@ -963,7 +901,7 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
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for (i = 0; i <= tex->buffer.b.b.last_level; i++)
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u_log_printf(log,
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" Level[%i]: offset=%" PRIu64 ", slice_size=%" PRIu64 ", "
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" Level[%i]: offset=%" PRIu64 ", slice_size=%" PRIu64 ", "
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"npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
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"mode=%u, tiling_index = %u\n",
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i, tex->surface.u.legacy.level[i].offset,
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@@ -974,11 +912,9 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
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tex->surface.u.legacy.tiling_index[i]);
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if (tex->surface.has_stencil) {
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u_log_printf(log, " StencilLayout: tilesplit=%u\n",
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tex->surface.u.legacy.stencil_tile_split);
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for (i = 0; i <= tex->buffer.b.b.last_level; i++) {
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u_log_printf(log,
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" StencilLevel[%i]: offset=%" PRIu64 ", "
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" StencilLevel[%i]: offset=%" PRIu64 ", "
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"slice_size=%" PRIu64 ", npix_x=%u, "
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"npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
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"mode=%u, tiling_index = %u\n",
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