radv/rt: Stop forcing wave32 by setting compute_subgroup_size

We end up reporting the wrong subgroup size this way.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23572>

src/amd/ci/external/radv-navi22-aco-fails.txt

@@ -1,2 +0,0 @@
-
-dEQP-VK.subgroups.builtin_var.ray_tracing.subgroupsize,Fail

src/amd/ci/radv-navi21-aco-fails.txt

@@ -1,8 +1,6 @@
 # New CTS failures in 1.3.5.0
 dEQP-VK.pipeline.fast_linked_library.extended_dynamic_state.before_draw.line_stipple_enable,Fail
 
-dEQP-VK.subgroups.builtin_var.ray_tracing.subgroupsize,Fail
-
 # Test bug https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/4498
 dEQP-VK.fragment_shading_barycentric.weights.pipeline_topology_dynamic.msaa_interpolate_at_offset.triangle_fan.perspective,Fail
 dEQP-VK.fragment_shading_barycentric.weights.pipeline_topology_dynamic.msaa_interpolate_at_offset.triangle_list.perspective,Fail

src/amd/ci/radv-vangogh-aco-fails.txt

@@ -3,8 +3,6 @@ dEQP-VK.binding_model.ics_miss_buffers8_sets1,Crash
 
 dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.linear_interpolation.no_offset_2_samples,Fail
 
-dEQP-VK.subgroups.builtin_var.ray_tracing.subgroupsize,Fail
-
 # Test bug https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/4498
 dEQP-VK.fragment_shading_barycentric.weights.pipeline_topology_dynamic.msaa_interpolate_at_offset.triangle_fan.perspective,Fail
 dEQP-VK.fragment_shading_barycentric.weights.pipeline_topology_dynamic.msaa_interpolate_at_offset.triangle_list.perspective,Fail

src/amd/vulkan/radv_pipeline_rt.c

@@ -336,7 +336,7 @@ radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache,
    for (uint32_t i = 0; i < num_shaders; i++) {
       struct radv_pipeline_stage temp_stage = *stage;
       temp_stage.nir = shaders[i];
-      radv_nir_lower_rt_abi(temp_stage.nir, pCreateInfo, &temp_stage.args, pipeline_key, stack_size,
+      radv_nir_lower_rt_abi(temp_stage.nir, pCreateInfo, &temp_stage.args, &stage->info, stack_size,
                             i > 0);
       radv_optimize_nir(temp_stage.nir, pipeline_key->optimisations_disabled);
       radv_postprocess_nir(device, pipeline_layout, pipeline_key, MESA_SHADER_NONE, &temp_stage);
@@ -496,17 +496,6 @@ compute_rt_stack_size(const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
       2 * callable_size;
 }
 
-static struct radv_pipeline_key
-radv_generate_rt_pipeline_key(const struct radv_device *device,
-                              const struct radv_ray_tracing_pipeline *pipeline,
-                              VkPipelineCreateFlags flags)
-{
-   struct radv_pipeline_key key = radv_generate_pipeline_key(device, &pipeline->base.base, flags);
-   key.cs.compute_subgroup_size = device->physical_device->rt_wave_size;
-
-   return key;
-}
-
 static void
 combine_config(struct ac_shader_config *config, struct ac_shader_config *other)
 {
@@ -597,7 +586,7 @@ radv_rt_pipeline_create(VkDevice _device, VkPipelineCache _cache,
       goto fail;
 
    struct radv_pipeline_key key =
-      radv_generate_rt_pipeline_key(device, pipeline, pCreateInfo->flags);
+      radv_generate_pipeline_key(device, &pipeline->base.base, pCreateInfo->flags);
 
    radv_hash_rt_shaders(pipeline->sha1, pCreateInfo, &key, pipeline->groups,
                         radv_get_hash_flags(device, keep_statistic_info));

src/amd/vulkan/radv_rt_shader.c

@@ -1630,7 +1630,7 @@ select_next_shader(nir_builder *b, nir_ssa_def *shader_va, unsigned wave_size)
 
 void
 radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
-                      const struct radv_shader_args *args, const struct radv_pipeline_key *key,
+                      const struct radv_shader_args *args, const struct radv_shader_info *info,
                       uint32_t *stack_size, bool resume_shader)
 {
    nir_builder b;
@@ -1705,7 +1705,7 @@ radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateInfoKH
    /* select next shader */
    b.cursor = nir_after_cf_list(&impl->body);
    shader_va = nir_load_var(&b, vars.shader_va);
-   nir_ssa_def *next = select_next_shader(&b, shader_va, key->cs.compute_subgroup_size);
+   nir_ssa_def *next = select_next_shader(&b, shader_va, info->wave_size);
    ac_nir_store_arg(&b, &args->ac, args->ac.rt.shader_pc, next);
 
    /* store back all variables to registers */
@@ -1739,5 +1739,5 @@ radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateInfoKH
    NIR_PASS_V(shader, nir_lower_vars_to_ssa);
    if (shader->info.stage == MESA_SHADER_CLOSEST_HIT ||
        shader->info.stage == MESA_SHADER_INTERSECTION)
-      NIR_PASS_V(shader, lower_hit_attribs, NULL, key->cs.compute_subgroup_size);
+      NIR_PASS_V(shader, lower_hit_attribs, NULL, info->wave_size);
 }

src/amd/vulkan/radv_shader.h

@@ -584,7 +584,7 @@ nir_shader *radv_parse_rt_stage(struct radv_device *device,
                                 const struct radv_pipeline_key *key);
 
 void radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
-                           const struct radv_shader_args *args, const struct radv_pipeline_key *key,
+                           const struct radv_shader_args *args, const struct radv_shader_info *info,
                            uint32_t *stack_size, bool resume_shader);
 
 struct radv_pipeline_stage;

src/amd/vulkan/radv_shader_info.c

@@ -362,8 +362,7 @@ radv_get_ballot_bit_size(struct radv_device *device, gl_shader_stage stage,
 {
    if (stage == MESA_SHADER_COMPUTE && info->cs.subgroup_size)
       return info->cs.subgroup_size;
-   else if (gl_shader_stage_is_rt(stage))
-      return device->physical_device->rt_wave_size;
+
    return 64;
 }