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radeonsi: prepare depth export registers at compile time

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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák
2014-05-06 19:59:53 +02:00
parent 9baaa5dd4f
commit d9e102b220
3 changed files with 14 additions and 14 deletions
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src/gallium/drivers/radeonsi/si_shader.c
+8
View File
@@ -1413,6 +1413,7 @@ static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
mask |= 0x1;
si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
}
if (stencil_index >= 0) {
@@ -1422,8 +1423,15 @@ static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
* breaks some stencil piglit tests
*/
mask |= 0x3;
si_shader_ctx->shader->db_shader_control |=
S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
}
if (stencil_index >= 0)
si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
else
si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
/* Specify which components to enable */
args[0] = lp_build_const_int32(base->gallivm, mask);
src/gallium/drivers/radeonsi/si_shader.h
+2
View File
@@ -179,6 +179,8 @@ struct si_pipe_shader {
unsigned lds_size;
unsigned spi_ps_input_ena;
unsigned spi_shader_col_format;
unsigned spi_shader_z_format;
unsigned db_shader_control;
unsigned cb_shader_mask;
bool cb0_is_integer;
unsigned sprite_coord_enable;
src/gallium/drivers/radeonsi/si_state_draw.c
+4 -14
View File
@@ -233,7 +233,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
struct si_pm4_state *pm4;
unsigned i, spi_ps_in_control, db_shader_control;
unsigned num_sgprs, num_user_sgprs;
unsigned spi_baryc_cntl = 0, spi_ps_input_ena, spi_shader_z_format;
unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
uint64_t va;
si_pm4_delete_state(sctx, ps, shader->pm4);
@@ -264,12 +264,8 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
}
}
for (i = 0; i < shader->shader.noutput; i++) {
if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
}
db_shader_control |= shader->db_shader_control;
if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
db_shader_control |= S_02880C_KILL_ENABLE(1);
@@ -292,13 +288,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
spi_shader_z_format = V_028710_SPI_SHADER_32_R;
else
spi_shader_z_format = 0;
si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
shader->spi_shader_col_format);
si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);