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i965g: first compiling file

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This commit is contained in:
Keith Whitwell
2009-10-24 11:53:43 +01:00
parent c93d2e4540
commit d71af266df
5 changed files with 114 additions and 35 deletions
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src/gallium/drivers/i965/brw_cc.c
+70 -26
View File
@@ -34,15 +34,41 @@
#include "brw_state.h"
#include "brw_defines.h"
struct sane_viewport {
float top;
float left;
float width;
float height;
float near;
float far;
};
static void calc_sane_viewport( const struct pipe_viewport_state *vp,
struct sane_viewport *svp )
{
/* XXX fix me, obviously.
*/
svp->top = 0;
svp->left = 0;
svp->width = 250;
svp->height = 250;
svp->near = 0;
svp->far = 1;
}
static void prepare_cc_vp( struct brw_context *brw )
{
struct brw_cc_viewport ccv;
struct sane_viewport svp;
memset(&ccv, 0, sizeof(ccv));
/* _NEW_VIEWPORT */
ccv.min_depth = ctx->Viewport.Near;
ccv.max_depth = ctx->Viewport.Far;
/* PIPE_NEW_VIEWPORT */
calc_sane_viewport( &brw->vp, &svp );
ccv.min_depth = svp.near;
ccv.max_depth = svp.far;
brw->sws->bo_unreference(brw->cc.vp_bo);
brw->cc.vp_bo = brw_cache_data( &brw->cache, BRW_CC_VP, &ccv, NULL, 0 );
@@ -58,21 +84,38 @@ const struct brw_tracked_state brw_cc_vp = {
};
struct brw_cc_unit_key {
struct pipe_depth_stencil_alpha_state dsa;
struct pipe_blend_state blend; /* no color mask */
struct brw_cc0 cc0;
struct brw_cc1 cc1;
struct brw_cc2 cc2;
struct brw_cc3 cc3;
struct brw_cc5 cc5;
struct brw_cc6 cc6;
struct brw_cc7 cc7;
};
static void
cc_unit_populate_key(struct brw_context *brw, struct brw_cc_unit_key *key)
/* A long-winded way to OR two unsigned integers together:
*/
static INLINE struct brw_cc3
combine_cc3( struct brw_cc3 a, struct brw_cc3 b )
{
memset(key, 0, sizeof(*key));
key->dsa = brw->dsa;
key->blend = brw->blend;
union { struct brw_cc3 cc3; unsigned i; } ca, cb;
ca.cc3 = a;
cb.cc3 = b;
ca.i |= cb.i;
return ca.cc3;
}
/* Clear non-respected values:
*/
key->blend.colormask = 0xf;
static void
cc_unit_populate_key(const struct brw_context *brw,
struct brw_cc_unit_key *key)
{
key->cc0 = brw->dsa->cc0;
key->cc1 = brw->dsa->cc1;
key->cc2 = brw->dsa->cc2;
key->cc3 = combine_cc3( brw->dsa->cc3, brw->blend->cc3 );
key->cc5 = brw->blend->cc5;
key->cc6 = brw->blend->cc6;
key->cc7 = brw->blend->cc7;
}
/**
@@ -86,16 +129,17 @@ cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key)
memset(&cc, 0, sizeof(cc));
cc.cc0 = brw->dsa.cc0;
cc.cc1 = brw->dsa.cc1;
cc.cc2 = brw->dsa.cc2;
cc.cc3 = brw->dsa.cc3 | brw->blend.cc3;
cc.cc0 = key->cc0;
cc.cc1 = key->cc1;
cc.cc2 = key->cc2;
cc.cc3 = key->cc3;
/* CACHE_NEW_CC_VP */
cc.cc4.cc_viewport_state_offset = brw->cc.vp_bo->offset >> 5; /* reloc */
cc.cc5 = brw->blend.cc5 | brw->debug.cc5;
cc.cc5 = key->cc5;
cc.cc6 = key->cc6;
cc.cc7 = key->cc7;
bo = brw_upload_cache(&brw->cache, BRW_CC_UNIT,
key, sizeof(*key),
@@ -104,12 +148,12 @@ cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key)
NULL, NULL);
/* Emit CC viewport relocation */
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION,
0,
0,
offsetof(struct brw_cc_unit_state, cc4),
brw->cc.vp_bo);
brw->sws->bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION,
0,
0,
offsetof(struct brw_cc_unit_state, cc4),
brw->cc.vp_bo);
return bo;
}
src/gallium/drivers/i965/brw_context.h
+30
View File
@@ -119,6 +119,33 @@
struct brw_context;
struct brw_depth_stencil_alpha_state {
struct pipe_depth_stencil_alpha_state templ; /* for draw module */
/* Precalculated hardware state:
*/
struct brw_cc0 cc0;
struct brw_cc1 cc1;
struct brw_cc2 cc2;
struct brw_cc3 cc3;
};
struct brw_blend_state {
struct pipe_depth_stencil_alpha_state templ; /* for draw module */
/* Precalculated hardware state:
*/
struct brw_cc3 cc3;
struct brw_cc5 cc5;
struct brw_cc6 cc6;
struct brw_cc7 cc7;
};
#define PIPE_NEW_DEPTH_STENCIL_ALPHA 0x1
#define PIPE_NEW_RAST 0x2
#define PIPE_NEW_BLEND 0x2
@@ -440,6 +467,9 @@ struct brw_context
const struct gl_vertex_program *vertex_program;
const struct gl_fragment_program *fragment_program;
struct pipe_framebuffer_state fb;
struct brw_depth_stencil_alpha_state *dsa;
struct brw_blend_state *blend;
struct pipe_viewport_state vp;
struct {
struct brw_state_flags dirty;
src/gallium/drivers/i965/brw_pipe_blend.c
+4
View File
@@ -1,4 +1,5 @@
/* _NEW_COLOR */
if (key->logic_op != GL_COPY) {
cc.cc2.logicop_enable = 1;
@@ -39,3 +40,6 @@
cc.cc6.x_dither_offset = 0;
}
if (INTEL_DEBUG & DEBUG_STATS)
cc.cc5.statistics_enable = 1;
}
src/gallium/drivers/i965/brw_state.h
+2 -1
View File
@@ -34,11 +34,12 @@
#define BRW_STATE_H
#include "brw_context.h"
#include "util/u_memory.h"
static inline void
brw_add_validated_bo(struct brw_context *brw, struct brw_winsys_buffer *bo)
{
assert(brw->state.validated_bo_count < ARRAY_SIZE(brw->state.validated_bos));
assert(brw->state.validated_bo_count < Elements(brw->state.validated_bos));
if (bo != NULL) {
brw->sws->bo_reference(bo);
src/gallium/drivers/i965/brw_structs.h
+8 -8
View File
@@ -663,7 +663,7 @@ struct brw_clip_unit_state
struct brw_cc_unit_state
{
struct
struct brw_cc0
{
GLuint pad0:3;
GLuint bf_stencil_pass_depth_pass_op:3;
@@ -681,7 +681,7 @@ struct brw_cc_unit_state
} cc0;
struct
struct brw_cc1
{
GLuint bf_stencil_ref:8;
GLuint stencil_write_mask:8;
@@ -690,7 +690,7 @@ struct brw_cc_unit_state
} cc1;
struct
struct brw_cc2
{
GLuint logicop_enable:1;
GLuint pad0:10;
@@ -702,7 +702,7 @@ struct brw_cc_unit_state
} cc2;
struct
struct brw_cc3
{
GLuint pad0:8;
GLuint alpha_test_func:3;
@@ -714,13 +714,13 @@ struct brw_cc_unit_state
GLuint pad2:16;
} cc3;
struct
struct brw_cc4
{
GLuint pad0:5;
GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
} cc4;
struct
struct brw_cc5
{
GLuint pad0:2;
GLuint ia_dest_blend_factor:5;
@@ -732,7 +732,7 @@ struct brw_cc_unit_state
GLuint dither_enable:1;
} cc5;
struct
struct brw_cc6
{
GLuint clamp_post_alpha_blend:1;
GLuint clamp_pre_alpha_blend:1;
@@ -745,7 +745,7 @@ struct brw_cc_unit_state
GLuint blend_function:3;
} cc6;
struct {
struct brw_cc7 {
union {
GLfloat f;
GLubyte ub[4];