freedreno/a6xx: Split clear and blit texture into different functions
Now that most of the state programming is in shareable helpers, we can split emit_blit_or_clear_texture into emit_blit_texture and fd6_clear_surface. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5717>
This commit is contained in:
Kristian H. Kristensen
committed by
Marge Bot
Marge Bot
parent
f383b2c18a
commit
d5c82c3c5f
@@ -512,13 +512,12 @@ emit_blit_src(struct fd_ringbuffer *ring, const struct pipe_blit_info *info, uns
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}
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static void
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emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
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const struct pipe_blit_info *info, union pipe_color_union *color)
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emit_blit_texture(struct fd_context *ctx,
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struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
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{
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const struct pipe_box *sbox = &info->src.box;
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const struct pipe_box *dbox = &info->dst.box;
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struct fd_resource *dst;
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enum a6xx_format dfmt;
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int sx1, sy1, sx2, sy2;
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int dx1, dy1, dx2, dy2;
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@@ -534,22 +533,18 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
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dst = fd_resource(info->dst.resource);
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dfmt = fd6_pipe2color(info->dst.format);
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uint32_t nr_samples = fd_resource_nr_samples(&dst->base);
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if (!color) {
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sx1 = sbox->x * nr_samples;
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sy1 = sbox->y;
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sx2 = (sbox->x + sbox->width) * nr_samples - 1;
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sy2 = sbox->y + sbox->height - 1;
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sx1 = sbox->x * nr_samples;
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sy1 = sbox->y;
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sx2 = (sbox->x + sbox->width) * nr_samples - 1;
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sy2 = sbox->y + sbox->height - 1;
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OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
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OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sx1));
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OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sx2));
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OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(sy1));
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OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(sy2));
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}
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OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
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OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sx1));
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OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sx2));
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OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(sy1));
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OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(sy2));
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dx1 = dbox->x * nr_samples;
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dy1 = dbox->y;
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@@ -560,52 +555,6 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
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OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dx1) | A6XX_GRAS_2D_DST_TL_Y(dy1));
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OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dx2) | A6XX_GRAS_2D_DST_BR_Y(dy2));
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if (color) {
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switch (info->dst.format) {
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case PIPE_FORMAT_Z24X8_UNORM:
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case PIPE_FORMAT_Z24_UNORM_S8_UINT:
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case PIPE_FORMAT_X24S8_UINT: {
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uint32_t depth_unorm24 = color->f[0] * ((1u << 24) - 1);
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uint8_t stencil = color->ui[1];
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color->ui[0] = depth_unorm24 & 0xff;
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color->ui[1] = (depth_unorm24 >> 8) & 0xff;
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color->ui[2] = (depth_unorm24 >> 16) & 0xff;
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color->ui[3] = stencil;
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break;
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}
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default:
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break;
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}
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OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
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switch (fd6_ifmt(dfmt)) {
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case R2D_UNORM8:
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case R2D_UNORM8_SRGB:
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OUT_RING(ring, float_to_ubyte(color->f[0]));
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OUT_RING(ring, float_to_ubyte(color->f[1]));
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OUT_RING(ring, float_to_ubyte(color->f[2]));
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OUT_RING(ring, float_to_ubyte(color->f[3]));
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break;
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case R2D_FLOAT16:
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OUT_RING(ring, _mesa_float_to_half(color->f[0]));
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OUT_RING(ring, _mesa_float_to_half(color->f[1]));
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OUT_RING(ring, _mesa_float_to_half(color->f[2]));
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OUT_RING(ring, _mesa_float_to_half(color->f[3]));
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break;
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case R2D_FLOAT32:
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case R2D_INT32:
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case R2D_INT16:
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case R2D_INT8:
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default:
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OUT_RING(ring, color->ui[0]);
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OUT_RING(ring, color->ui[1]);
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OUT_RING(ring, color->ui[2]);
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OUT_RING(ring, color->ui[3]);
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break;
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}
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}
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if (info->scissor_enable) {
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OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
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OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.minx) |
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@@ -614,13 +563,11 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
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A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.maxy - 1));
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}
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emit_blit_setup(ring, info->dst.format, info->scissor_enable, color);
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emit_blit_setup(ring, info->dst.format, info->scissor_enable, NULL);
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for (unsigned i = 0; i < info->dst.box.depth; i++) {
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if (!color)
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emit_blit_src(ring, info, sbox->z + i, nr_samples);
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emit_blit_src(ring, info, sbox->z + i, nr_samples);
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emit_blit_dst(ring, info->dst.resource, info->dst.format, info->dst.level, dbox->z + i);
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/*
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@@ -643,28 +590,95 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
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}
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}
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static void
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emit_clear_color(struct fd_ringbuffer *ring,
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enum pipe_format pfmt, union pipe_color_union *color)
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{
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switch (pfmt) {
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case PIPE_FORMAT_Z24X8_UNORM:
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case PIPE_FORMAT_Z24_UNORM_S8_UINT:
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case PIPE_FORMAT_X24S8_UINT: {
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uint32_t depth_unorm24 = color->f[0] * ((1u << 24) - 1);
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uint8_t stencil = color->ui[1];
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color->ui[0] = depth_unorm24 & 0xff;
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color->ui[1] = (depth_unorm24 >> 8) & 0xff;
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color->ui[2] = (depth_unorm24 >> 16) & 0xff;
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color->ui[3] = stencil;
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break;
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}
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default:
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break;
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}
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OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
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switch (fd6_ifmt(fd6_pipe2color(pfmt))) {
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case R2D_UNORM8:
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case R2D_UNORM8_SRGB:
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OUT_RING(ring, float_to_ubyte(color->f[0]));
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OUT_RING(ring, float_to_ubyte(color->f[1]));
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OUT_RING(ring, float_to_ubyte(color->f[2]));
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OUT_RING(ring, float_to_ubyte(color->f[3]));
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break;
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case R2D_FLOAT16:
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OUT_RING(ring, _mesa_float_to_half(color->f[0]));
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OUT_RING(ring, _mesa_float_to_half(color->f[1]));
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OUT_RING(ring, _mesa_float_to_half(color->f[2]));
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OUT_RING(ring, _mesa_float_to_half(color->f[3]));
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break;
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case R2D_FLOAT32:
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case R2D_INT32:
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case R2D_INT16:
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case R2D_INT8:
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default:
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OUT_RING(ring, color->ui[0]);
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OUT_RING(ring, color->ui[1]);
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OUT_RING(ring, color->ui[2]);
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OUT_RING(ring, color->ui[3]);
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break;
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}
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}
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void
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fd6_clear_surface(struct fd_context *ctx,
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struct fd_ringbuffer *ring, struct pipe_surface *psurf,
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uint32_t width, uint32_t height, union pipe_color_union *color)
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{
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struct pipe_blit_info info = {};
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if (DEBUG_BLIT) {
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fprintf(stderr, "surface clear:\ndst resource: ");
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util_dump_resource(stderr, psurf->texture);
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fprintf(stderr, "\n");
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}
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info.dst.resource = psurf->texture;
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info.dst.level = psurf->u.tex.level;
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info.dst.box.x = 0;
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info.dst.box.y = 0;
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info.dst.box.z = psurf->u.tex.first_layer;
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info.dst.box.width = width;
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info.dst.box.height = height;
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info.dst.box.depth = psurf->u.tex.last_layer + 1 - psurf->u.tex.first_layer;
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info.dst.format = psurf->format;
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info.src = info.dst;
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info.mask = util_format_get_mask(psurf->format);
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info.filter = PIPE_TEX_FILTER_NEAREST;
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info.scissor_enable = 0;
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uint32_t nr_samples = fd_resource_nr_samples(psurf->texture);
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OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
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OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
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OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(width * nr_samples - 1) |
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A6XX_GRAS_2D_DST_BR_Y(height - 1));
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emit_blit_or_clear_texture(ctx, ring, &info, color);
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emit_clear_color(ring, psurf->format, color);
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emit_blit_setup(ring, psurf->format, false, color);
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for (unsigned i = psurf->u.tex.first_layer; i <= psurf->u.tex.last_layer; i++) {
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emit_blit_dst(ring, psurf->texture, psurf->format, psurf->u.tex.level, i);
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/*
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* Blit command:
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*/
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OUT_PKT7(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, 0x3f);
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OUT_WFI5(ring);
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OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
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OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
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OUT_PKT7(ring, CP_BLIT, 1);
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OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
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OUT_WFI5(ring);
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OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
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OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
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}
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}
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static bool
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@@ -713,7 +727,7 @@ handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
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debug_assert(info->src.resource->target != PIPE_BUFFER);
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debug_assert(info->dst.resource->target != PIPE_BUFFER);
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fd_log(batch, "START BLIT (TEXTURE)");
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emit_blit_or_clear_texture(ctx, batch->draw, info, NULL);
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emit_blit_texture(ctx, batch->draw, info);
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fd_log(batch, "END BLIT (TEXTURE)");
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}
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