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ir3: Drop write_mask handling

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It's all scalar SSA.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
This commit is contained in:
Alyssa Rosenzweig
2023-08-01 14:22:08 -04:00
committed by Marge Bot
parent 7be895f960
commit d550dea819
1 changed files with 3 additions and 2 deletions
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src/freedreno/ir3/ir3_compiler_nir.c
+3 -2
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@@ -426,11 +426,12 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
}
/* General case: We can just grab the one used channel per src. */
assert(nir_dest_num_components(alu->dest.dest) == 1);
for (int i = 0; i < info->num_inputs; i++) {
unsigned chan = ffs(alu->dest.write_mask) - 1;
nir_alu_src *asrc = &alu->src[i];
src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
bs[i] = nir_src_bit_size(asrc->src);
compile_assert(ctx, src[i]);