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nvfx: switch to rules-ng-ng register headers

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This is the new register generation toolkit in use by nouveau.

As far as I know, this is the best register description toolkit in
existence, and you should use it too for your hardware :)

Thanks to Marcin Kościelnicki for inventing it and performing
invaluable reverse engineering work of nVidia chips.
This commit is contained in:
Luca Barbieri
2010-09-05 10:10:09 +02:00
parent 3bca263a92
commit d46c5ce7b6
18 changed files with 2587 additions and 334 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/nouveau/nv_object.xml.h
+231
View File
@@ -0,0 +1,231 @@
#ifndef NV_OBJECT_XML
#define NV_OBJECT_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
- nv30-40_3d.xml ( 31709 bytes, from 2010-09-05 07:53:14)
- copyright.xml ( 6503 bytes, from 2010-04-10 23:15:50)
- nv_3ddefs.xml ( 15193 bytes, from 2010-09-05 07:50:15)
- nv_defs.xml ( 4437 bytes, from 2010-08-05 19:38:53)
- nv_object.xml ( 10424 bytes, from 2010-08-05 19:38:53)
- nvchipsets.xml ( 2824 bytes, from 2010-08-05 19:38:53)
Copyright (C) 2006-2010 by the following authors:
- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
- Ben Skeggs (darktama, darktama_)
- B. R. <koala_br@users.sourceforge.net> (koala_br)
- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
- Dmitry Baryshkov
- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
- EdB <edb_@users.sf.net> (edb_)
- Erik Waling <erikwailing@users.sf.net> (erikwaling)
- Francisco Jerez <currojerez@riseup.net> (curro, curro_, currojerez)
- imirkin <imirkin@users.sf.net> (imirkin)
- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
- Mark Carey <mark.carey@gmail.com> (careym)
- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
- Patrice Mandin <mandin.patrice@orange.fr> (pmandin, pmdata)
- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
- Peter Popov <ironpeter@users.sf.net> (ironpeter)
- Richard Hughes <hughsient@users.sf.net> (hughsient)
- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
- Serge Martin
- Simon Raffeiner
- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
- sturmflut <sturmflut@users.sf.net> (sturmflut)
- Sylvain Munaut <tnt@246tNt.com>
- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
- Younes Manton <younes.m@gmail.com> (ymanton)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define NV01_ROOT 0x00000001
#define NV01_CONTEXT_DMA 0x00000002
#define NV01_DEVICE 0x00000003
#define NV01_TIMER 0x00000004
#define NV01_NULL 0x00000030
#define NV01_MEMORY_LOCAL_BANKED 0x0000003d
#define NV01_MAPPING_SYSTEM 0x0000003e
#define NV03_MEMORY_LOCAL_CURSOR 0x0000003f
#define NV01_MEMORY_LOCAL_LINEAR 0x00000040
#define NV01_MAPPING_LOCAL 0x00000041
#define NV03_VIDEO_LUT_CURSOR_DAC 0x00000046
#define NV03_CHANNEL_PIO 0x0000006a
#define NV03_CHANNEL_DMA 0x0000006b
#define NV10_VIDEO_DISPLAY 0x0000007c
#define NV01_CONTEXT_BETA1 0x00000012
#define NV04_BETA_SOLID 0x00000072
#define NV01_CONTEXT_COLOR_KEY 0x00000017
#define NV04_CONTEXT_COLOR_KEY 0x00000057
#define NV01_CONTEXT_PATTERN 0x00000018
#define NV01_CONTEXT_CLIP_RECTANGLE 0x00000019
#define NV03_CONTEXT_ROP 0x00000043
#define NV04_IMAGE_PATTERN 0x00000044
#define NV01_RENDER_SOLID_LINE 0x0000001c
#define NV04_RENDER_SOLID_LINE 0x0000005c
#define NV30_RENDER_SOLID_LINE 0x0000035c
#define NV40_RENDER_SOLID_LINE 0x0000305c
#define NV01_RENDER_SOLID_TRIANGLE 0x0000001d
#define NV04_RENDER_SOLID_TRIANGLE 0x0000005d
#define NV01_RENDER_SOLID_RECTANGLE 0x0000001e
#define NV04_RENDER_SOLID_RECTANGLE 0x0000005e
#define NV01_IMAGE_BLIT 0x0000001f
#define NV04_IMAGE_BLIT 0x0000005f
#define NV11_IMAGE_BLIT 0x0000009f
#define NV01_IMAGE_FROM_CPU 0x00000021
#define NV04_IMAGE_FROM_CPU 0x00000061
#define NV05_IMAGE_FROM_CPU 0x00000065
#define NV10_IMAGE_FROM_CPU 0x0000008a
#define NV30_IMAGE_FROM_CPU 0x0000038a
#define NV40_IMAGE_FROM_CPU 0x0000308a
#define NV03_STRETCHED_IMAGE_FROM_CPU 0x00000036
#define NV04_STRETCHED_IMAGE_FROM_CPU 0x00000076
#define NV05_STRETCHED_IMAGE_FROM_CPU 0x00000066
#define NV30_STRETCHED_IMAGE_FROM_CPU 0x00000366
#define NV40_STRETCHED_IMAGE_FROM_CPU 0x00003066
#define NV03_SCALED_IMAGE_FROM_MEMORY 0x00000037
#define NV04_SCALED_IMAGE_FROM_MEMORY 0x00000077
#define NV05_SCALED_IMAGE_FROM_MEMORY 0x00000063
#define NV10_SCALED_IMAGE_FROM_MEMORY 0x00000089
#define NV30_SCALED_IMAGE_FROM_MEMORY 0x00000389
#define NV40_SCALED_IMAGE_FROM_MEMORY 0x00003089
#define NV50_SCALED_IMAGE_FROM_MEMORY 0x00005089
#define NV04_DVD_SUBPICTURE 0x00000038
#define NV10_DVD_SUBPICTURE 0x00000088
#define NV03_GDI_RECTANGLE_TEXT 0x0000004b
#define NV04_GDI_RECTANGLE_TEXT 0x0000004a
#define NV04_SWIZZLED_SURFACE 0x00000052
#define NV11_SWIZZLED_SURFACE 0x0000009e
#define NV30_SWIZZLED_SURFACE 0x0000039e
#define NV40_SWIZZLED_SURFACE 0x0000309e
#define NV03_CONTEXT_SURFACE_DST 0x00000058
#define NV03_CONTEXT_SURFACE_SRC 0x00000059
#define NV04_CONTEXT_SURFACES_2D 0x00000042
#define NV10_CONTEXT_SURFACES_2D 0x00000062
#define NV30_CONTEXT_SURFACES_2D 0x00000362
#define NV40_CONTEXT_SURFACES_2D 0x00003062
#define NV50_CONTEXT_SURFACES_2D 0x00005062
#define NV04_INDEXED_IMAGE_FROM_CPU 0x00000060
#define NV05_INDEXED_IMAGE_FROM_CPU 0x00000064
#define NV30_INDEXED_IMAGE_FROM_CPU 0x00000364
#define NV40_INDEXED_IMAGE_FROM_CPU 0x00003064
#define NV10_TEXTURE_FROM_CPU 0x0000007b
#define NV30_TEXTURE_FROM_CPU 0x0000037b
#define NV40_TEXTURE_FROM_CPU 0x0000307b
#define NV04_M2MF 0x00000039
#define NV50_M2MF 0x00005039
#define NVC0_M2MF 0x00009039
#define NV03_TEXTURED_TRIANGLE 0x00000048
#define NV04_TEXTURED_TRIANGLE 0x00000054
#define NV10_TEXTURED_TRIANGLE 0x00000094
#define NV04_MULTITEX_TRIANGLE 0x00000055
#define NV10_MULTITEX_TRIANGLE 0x00000095
#define NV03_CONTEXT_SURFACE_COLOR 0x0000005a
#define NV03_CONTEXT_SURFACE_ZETA 0x0000005b
#define NV04_CONTEXT_SURFACES_3D 0x00000053
#define NV10_CONTEXT_SURFACES_3D 0x00000093
#define NV10_3D 0x00000056
#define NV11_3D 0x00000096
#define NV17_3D 0x00000099
#define NV20_3D 0x00000097
#define NV25_3D 0x00000597
#define NV30_3D 0x00000397
#define NV35_3D 0x00000497
#define NV34_3D 0x00000697
#define NV40_3D 0x00004097
#define NV44_3D 0x00004497
#define NV50_3D 0x00005097
#define NV84_3D 0x00008297
#define NVA0_3D 0x00008397
#define NVA3_3D 0x00008597
#define NVAF_3D 0x00008697
#define NVC0_3D 0x00009097
#define NV50_2D 0x0000502d
#define NVC0_2D 0x0000902d
#define NV50_COMPUTE 0x000050c0
#define NVA3_COMPUTE 0x000085c0
#define NVC0_COMPUTE 0x000090c0
#define NV01_SUBCHAN__SIZE 0x00002000
#define NV01_SUBCHAN 0x00000000
#define NV01_SUBCHAN_OBJECT 0x00000000
#define NV84_SUBCHAN_QUERY_ADDRESS_HIGH 0x00000010
#define NV84_SUBCHAN_QUERY_ADDRESS_LOW 0x00000014
#define NV84_SUBCHAN_QUERY_COUNTER 0x00000018
#define NV84_SUBCHAN_QUERY_GET 0x0000001c
#define NV84_SUBCHAN_UNK20 0x00000020
#define NV84_SUBCHAN_UNK24 0x00000024
#define NV10_SUBCHAN_REF_CNT 0x00000050
#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
#define NV50_SUBCHAN_UNK80 0x00000080
#define NV01_GRAPH 0x00000000
#define NV04_GRAPH_NOP 0x00000100
#define NV01_GRAPH_NOTIFY 0x00000104
#define NV01_GRAPH_NOTIFY_WRITE 0x00000000
#define NV01_GRAPH_NOTIFY_WRITE_AND_AWAKEN 0x00000001
#define NV50_GRAPH_WAIT_FOR_IDLE 0x00000110
#define NVA3_GRAPH_UNK0120 0x00000120
#define NVA3_GRAPH_UNK0124 0x00000124
#define NV40_GRAPH_PM_TRIGGER 0x00000140
#endif /* NV_OBJECT_XML */
src/gallium/drivers/nvfx/nv30-40_3d.xml.h
+2022
View File
File diff suppressed because it is too large Load Diff
src/gallium/drivers/nvfx/nv30_fragtex.c
+12 -12
View File
@@ -14,11 +14,11 @@ nv30_sampler_state_init(struct pipe_context *pipe,
if (cso->max_anisotropy >= 2)
{
if (cso->max_anisotropy >= 8)
ps->en |= NV34TCL_TX_ENABLE_ANISO_8X;
ps->en |= NV30_3D_TEX_ENABLE_ANISO_8X;
else if (cso->max_anisotropy >= 4)
ps->en |= NV34TCL_TX_ENABLE_ANISO_4X;
ps->en |= NV30_3D_TEX_ENABLE_ANISO_4X;
else if (cso->max_anisotropy >= 2)
ps->en |= NV34TCL_TX_ENABLE_ANISO_2X;
ps->en |= NV30_3D_TEX_ENABLE_ANISO_2X;
}
limit = CLAMP(cso->lod_bias, -16.0, 15.0 + (255.0 / 256.0));
@@ -27,7 +27,7 @@ nv30_sampler_state_init(struct pipe_context *pipe,
ps->max_lod = (int)CLAMP(cso->max_lod, 0.0, 15.0);
ps->min_lod = (int)CLAMP(cso->min_lod, 0.0, 15.0);
ps->en |= NV34TCL_TX_ENABLE_ENABLE;
ps->en |= NV30_3D_TEX_ENABLE_ENABLE;
}
void
@@ -42,10 +42,10 @@ nv30_sampler_view_init(struct pipe_context *pipe,
assert(tf->fmt[0] >= 0);
txf = sv->u.init_fmt;
txf |= (level != sv->base.last_level ? NV34TCL_TX_FORMAT_MIPMAP : 0);
txf |= util_logbase2(u_minify(pt->width0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_U_SHIFT;
txf |= util_logbase2(u_minify(pt->height0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_V_SHIFT;
txf |= util_logbase2(u_minify(pt->depth0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_W_SHIFT;
txf |= (level != sv->base.last_level ? NV30_3D_TEX_FORMAT_MIPMAP : 0);
txf |= util_logbase2(u_minify(pt->width0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_U__SHIFT;
txf |= util_logbase2(u_minify(pt->height0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_V__SHIFT;
txf |= util_logbase2(u_minify(pt->depth0, level)) << NV30_3D_TEX_FORMAT_BASE_SIZE_W__SHIFT;
txf |= 0x10000;
sv->u.nv30.fmt[0] = tf->fmt[0] | txf;
@@ -53,7 +53,7 @@ nv30_sampler_view_init(struct pipe_context *pipe,
sv->u.nv30.fmt[2] = tf->fmt[2] | txf;
sv->u.nv30.fmt[3] = tf->fmt[3] | txf;
sv->swizzle |= (nvfx_subresource_pitch(pt, 0) << NV34TCL_TX_SWIZZLE_RECT_PITCH_SHIFT);
sv->swizzle |= (nvfx_subresource_pitch(pt, 0) << NV30_3D_TEX_SWIZZLE_RECT_PITCH__SHIFT);
if(pt->height0 <= 1 || util_format_is_compressed(sv->base.format))
sv->u.nv30.rect = -1;
@@ -102,13 +102,13 @@ nv30_fragtex_set(struct nvfx_context *nvfx, int unit)
txf = sv->u.nv30.fmt[ps->compare + (use_rect ? 2 : 0)];
MARK_RING(chan, 9, 2);
OUT_RING(chan, RING_3D(NV34TCL_TX_OFFSET(unit), 8));
OUT_RING(chan, RING_3D(NV30_3D_TEX_OFFSET(unit), 8));
OUT_RELOC(chan, bo, sv->offset, tex_flags | NOUVEAU_BO_LOW, 0, 0);
OUT_RELOC(chan, bo, txf,
tex_flags | NOUVEAU_BO_OR,
NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1);
NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1);
OUT_RING(chan, (ps->wrap & sv->wrap_mask) | sv->wrap);
OUT_RING(chan, ps->en | (min_lod << NV34TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT) | (max_lod << NV34TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT));
OUT_RING(chan, ps->en | (min_lod << NV30_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT) | (max_lod << NV30_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT));
OUT_RING(chan, sv->swizzle);
OUT_RING(chan, ps->filt | sv->filt);
OUT_RING(chan, sv->npot_size);
src/gallium/drivers/nvfx/nv40_fragtex.c
+15 -15
View File
@@ -14,19 +14,19 @@ nv40_sampler_state_init(struct pipe_context *pipe,
ps->wrap |= (1 << 5);
if (cso->max_anisotropy >= 16)
ps->en |= NV40TCL_TEX_ENABLE_ANISO_16X;
ps->en |= NV40_3D_TEX_ENABLE_ANISO_16X;
else if (cso->max_anisotropy >= 12)
ps->en |= NV40TCL_TEX_ENABLE_ANISO_12X;
ps->en |= NV40_3D_TEX_ENABLE_ANISO_12X;
else if (cso->max_anisotropy >= 10)
ps->en |= NV40TCL_TEX_ENABLE_ANISO_10X;
ps->en |= NV40_3D_TEX_ENABLE_ANISO_10X;
else if (cso->max_anisotropy >= 8)
ps->en |= NV40TCL_TEX_ENABLE_ANISO_8X;
ps->en |= NV40_3D_TEX_ENABLE_ANISO_8X;
else if (cso->max_anisotropy >= 6)
ps->en |= NV40TCL_TEX_ENABLE_ANISO_6X;
ps->en |= NV40_3D_TEX_ENABLE_ANISO_6X;
else if (cso->max_anisotropy >= 4)
ps->en |= NV40TCL_TEX_ENABLE_ANISO_4X;
ps->en |= NV40_3D_TEX_ENABLE_ANISO_4X;
else
ps->en |= NV40TCL_TEX_ENABLE_ANISO_2X;
ps->en |= NV40_3D_TEX_ENABLE_ANISO_2X;
}
limit = CLAMP(cso->lod_bias, -16.0, 15.0 + (255.0 / 256.0));
@@ -35,7 +35,7 @@ nv40_sampler_state_init(struct pipe_context *pipe,
ps->max_lod = (int)(CLAMP(cso->max_lod, 0.0, 15.0 + (255.0 / 256.0)) * 256.0);
ps->min_lod = (int)(CLAMP(cso->min_lod, 0.0, 15.0 + (255.0 / 256.0)) * 256.0);
ps->en |= NV40TCL_TEX_ENABLE_ENABLE;
ps->en |= NV40_3D_TEX_ENABLE_ENABLE;
}
void
@@ -52,21 +52,21 @@ nv40_sampler_view_init(struct pipe_context *pipe,
txf = sv->u.init_fmt;
txf |= 0x8000;
if(pt->target == PIPE_TEXTURE_CUBE)
txf |= ((pt->last_level + 1) << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT);
txf |= ((pt->last_level + 1) << NV40_3D_TEX_FORMAT_MIPMAP_COUNT__SHIFT);
else
txf |= (((sv->base.last_level - sv->base.first_level) + 1) << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT);
txf |= (((sv->base.last_level - sv->base.first_level) + 1) << NV40_3D_TEX_FORMAT_MIPMAP_COUNT__SHIFT);
if (!mt->linear_pitch)
sv->u.nv40.npot_size2 = 0;
else {
sv->u.nv40.npot_size2 = mt->linear_pitch;
txf |= NV40TCL_TEX_FORMAT_LINEAR;
txf |= NV40_3D_TEX_FORMAT_LINEAR;
}
sv->u.nv40.fmt[0] = tf->fmt[4] | txf;
sv->u.nv40.fmt[1] = tf->fmt[5] | txf;
sv->u.nv40.npot_size2 |= (u_minify(pt->depth0, level) << NV40TCL_TEX_SIZE1_DEPTH_SHIFT);
sv->u.nv40.npot_size2 |= (u_minify(pt->depth0, level) << NV40_3D_TEX_SIZE1_DEPTH__SHIFT);
sv->lod_offset = (sv->base.first_level - level) * 256;
sv->max_lod_limit = (sv->base.last_level - level) * 256;
@@ -87,17 +87,17 @@ nv40_fragtex_set(struct nvfx_context *nvfx, int unit)
txf = sv->u.nv40.fmt[ps->compare] | ps->fmt;
MARK_RING(chan, 11, 2);
OUT_RING(chan, RING_3D(NV34TCL_TX_OFFSET(unit), 8));
OUT_RING(chan, RING_3D(NV30_3D_TEX_OFFSET(unit), 8));
OUT_RELOC(chan, bo, sv->offset, tex_flags | NOUVEAU_BO_LOW, 0, 0);
OUT_RELOC(chan, bo, txf, tex_flags | NOUVEAU_BO_OR,
NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1);
NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1);
OUT_RING(chan, (ps->wrap & sv->wrap_mask) | sv->wrap);
OUT_RING(chan, ps->en | (min_lod << 19) | (max_lod << 7));
OUT_RING(chan, sv->swizzle);
OUT_RING(chan, ps->filt | sv->filt);
OUT_RING(chan, sv->npot_size);
OUT_RING(chan, ps->bcol);
OUT_RING(chan, RING_3D(NV40TCL_TEX_SIZE1(unit), 1));
OUT_RING(chan, RING_3D(NV40_3D_TEX_SIZE1(unit), 1));
OUT_RING(chan, sv->u.nv40.npot_size2);
nvfx->hw_txf[unit] = txf;
src/gallium/drivers/nvfx/nvfx_context.h
+5 -5
View File
@@ -18,7 +18,7 @@
#include "nouveau/nouveau_winsys.h"
#include "nouveau/nouveau_gldefs.h"
#include "nv30-40_3d.xml.h"
#include "nvfx_state.h"
#define NOUVEAU_ERR(fmt, args...) \
@@ -343,25 +343,25 @@ static inline void nvfx_emit_vtx_attr(struct nouveau_channel* chan, unsigned att
{
switch (ncomp) {
case 4:
OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_4F_X(attrib), 4));
OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_4F_X(attrib), 4));
OUT_RING(chan, fui(v[0]));
OUT_RING(chan, fui(v[1]));
OUT_RING(chan, fui(v[2]));
OUT_RING(chan, fui(v[3]));
break;
case 3:
OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_3F_X(attrib), 3));
OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_3F_X(attrib), 3));
OUT_RING(chan, fui(v[0]));
OUT_RING(chan, fui(v[1]));
OUT_RING(chan, fui(v[2]));
break;
case 2:
OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_2F_X(attrib), 2));
OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_2F_X(attrib), 2));
OUT_RING(chan, fui(v[0]));
OUT_RING(chan, fui(v[1]));
break;
case 1:
OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_1F(attrib), 1));
OUT_RING(chan, RING_3D(NV30_3D_VTX_ATTR_1F(attrib), 1));
OUT_RING(chan, fui(v[0]));
break;
}
src/gallium/drivers/nvfx/nvfx_draw.c
+12 -12
View File
@@ -29,11 +29,11 @@ nvfx_render_flush(struct draw_stage *stage, unsigned flags)
struct nvfx_context *nvfx = rs->nvfx;
struct nouveau_channel *chan = nvfx->screen->base.channel;
if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) {
if (rs->prim != NV30_3D_VERTEX_BEGIN_END_STOP) {
assert(AVAIL_RING(chan) >= 2);
OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
OUT_RING(chan, NV34TCL_VERTEX_BEGIN_END_STOP);
rs->prim = NV34TCL_VERTEX_BEGIN_END_STOP;
OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1));
OUT_RING(chan, NV30_3D_VERTEX_BEGIN_END_STOP);
rs->prim = NV30_3D_VERTEX_BEGIN_END_STOP;
}
}
@@ -62,9 +62,9 @@ nvfx_render_prim(struct draw_stage *stage, struct prim_header *prim,
/* Switch primitive modes if necessary */
if (rs->prim != mode) {
if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) {
OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
OUT_RING(chan, NV34TCL_VERTEX_BEGIN_END_STOP);
if (rs->prim != NV30_3D_VERTEX_BEGIN_END_STOP) {
OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1));
OUT_RING(chan, NV30_3D_VERTEX_BEGIN_END_STOP);
}
/* XXX: any command a lot of times seems to (mostly) fix corruption that would otherwise happen */
@@ -79,12 +79,12 @@ nvfx_render_prim(struct draw_stage *stage, struct prim_header *prim,
}
}
OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1));
OUT_RING (chan, mode);
rs->prim = mode;
}
OUT_RING(chan, RING_3D_NI(NV34TCL_VERTEX_DATA, num_attribs * 4 * count));
OUT_RING(chan, RING_3D_NI(NV30_3D_VERTEX_DATA, num_attribs * 4 * count));
if(no_elements) {
OUT_RING(chan, 0);
OUT_RING(chan, 0);
@@ -107,19 +107,19 @@ nvfx_render_prim(struct draw_stage *stage, struct prim_header *prim,
static void
nvfx_render_point(struct draw_stage *draw, struct prim_header *prim)
{
nvfx_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_POINTS, 1);
nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_POINTS, 1);
}
static void
nvfx_render_line(struct draw_stage *draw, struct prim_header *prim)
{
nvfx_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_LINES, 2);
nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_LINES, 2);
}
static void
nvfx_render_tri(struct draw_stage *draw, struct prim_header *prim)
{
nvfx_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_TRIANGLES, 3);
nvfx_render_prim(draw, prim, NV30_3D_VERTEX_BEGIN_END_TRIANGLES, 3);
}
static void
src/gallium/drivers/nvfx/nvfx_fragprog.c
+14 -14
View File
@@ -205,7 +205,7 @@ nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn)
memset(hw, 0, sizeof(uint32_t) * 4);
if (insn.op == NVFX_FP_OP_OPCODE_KIL)
fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL;
fp->fp_control |= NV30_3D_FP_CONTROL_USES_KIL;
hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT);
hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT);
hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT);
@@ -1070,10 +1070,10 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
for (unsigned i = 0; i < pfp->info.num_properties; ++i) {
if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_ORIGIN) {
if(pfp->info.properties[i].data[0])
fp->coord_conventions |= NV34TCL_COORD_CONVENTIONS_ORIGIN_INVERTED;
fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED;
} else if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_PIXEL_CENTER) {
if(pfp->info.properties[i].data[0])
fp->coord_conventions |= NV34TCL_COORD_CONVENTIONS_CENTER_INTEGER;
fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_CENTER_INTEGER;
}
}
@@ -1124,7 +1124,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
if(!nvfx->is_nv4x)
fp->fp_control |= (fpc->num_regs-1)/2;
else
fp->fp_control |= fpc->num_regs << NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT;
fp->fp_control |= fpc->num_regs << NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT;
/* Terminate final instruction */
if(fp->insn)
@@ -1497,17 +1497,17 @@ update:
nvfx->hw_fragprog = fp;
MARK_RING(chan, 8, 1);
OUT_RING(chan, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1));
OUT_RING(chan, RING_3D(NV30_3D_FP_ACTIVE_PROGRAM, 1));
OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM |
NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
OUT_RING(chan, RING_3D(NV34TCL_FP_CONTROL, 1));
NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0,
NV30_3D_FP_ACTIVE_PROGRAM_DMA1);
OUT_RING(chan, RING_3D(NV30_3D_FP_CONTROL, 1));
OUT_RING(chan, fp->fp_control);
if(!nvfx->is_nv4x) {
OUT_RING(chan, RING_3D(NV34TCL_FP_REG_CONTROL, 1));
OUT_RING(chan, RING_3D(NV30_3D_FP_REG_CONTROL, 1));
OUT_RING(chan, (1<<16)|0x4);
OUT_RING(chan, RING_3D(NV34TCL_TX_UNITS_ENABLE, 1));
OUT_RING(chan, RING_3D(NV30_3D_TEX_UNITS_ENABLE, 1));
OUT_RING(chan, fp->samplers);
}
}
@@ -1517,7 +1517,7 @@ update:
if(pointsprite_control != nvfx->hw_pointsprite_control)
{
WAIT_RING(chan, 2);
OUT_RING(chan, RING_3D(NV34TCL_POINT_SPRITE, 1));
OUT_RING(chan, RING_3D(NV30_3D_POINT_SPRITE, 1));
OUT_RING(chan, pointsprite_control);
nvfx->hw_pointsprite_control = pointsprite_control;
}
@@ -1536,10 +1536,10 @@ nvfx_fragprog_relocate(struct nvfx_context *nvfx)
unsigned fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; // TODO: GART?
fp_flags |= NOUVEAU_BO_DUMMY;
MARK_RING(chan, 2, 2);
OUT_RELOC(chan, bo, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0);
OUT_RELOC(chan, bo, RING_3D(NV30_3D_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0);
OUT_RELOC(chan, bo, offset, fp_flags | NOUVEAU_BO_LOW |
NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0,
NV30_3D_FP_ACTIVE_PROGRAM_DMA1);
nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG;
}
src/gallium/drivers/nvfx/nvfx_fragtex.c
+42 -42
View File
@@ -12,12 +12,12 @@ nvfx_sampler_state_create(struct pipe_context *pipe,
ps = MALLOC(sizeof(struct nvfx_sampler_state));
/* on nv30, we use this as an internal flag */
ps->fmt = cso->normalized_coords ? 0 : NV40TCL_TEX_FORMAT_RECT;
ps->fmt = cso->normalized_coords ? 0 : NV40_3D_TEX_FORMAT_RECT;
ps->en = 0;
ps->filt = nvfx_tex_filter(cso) | 0x2000; /*voodoo*/
ps->wrap = (nvfx_tex_wrap_mode(cso->wrap_s) << NV34TCL_TX_WRAP_S_SHIFT) |
(nvfx_tex_wrap_mode(cso->wrap_t) << NV34TCL_TX_WRAP_T_SHIFT) |
(nvfx_tex_wrap_mode(cso->wrap_r) << NV34TCL_TX_WRAP_R_SHIFT);
ps->wrap = (nvfx_tex_wrap_mode(cso->wrap_s) << NV30_3D_TEX_WRAP_S__SHIFT) |
(nvfx_tex_wrap_mode(cso->wrap_t) << NV30_3D_TEX_WRAP_T__SHIFT) |
(nvfx_tex_wrap_mode(cso->wrap_r) << NV30_3D_TEX_WRAP_R__SHIFT);
ps->compare = FALSE;
if(cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
@@ -80,21 +80,21 @@ nvfx_create_sampler_view(struct pipe_context *pipe,
pipe_resource_reference(&sv->base.texture, pt);
sv->base.context = pipe;
txf = NV34TCL_TX_FORMAT_NO_BORDER;
txf = NV30_3D_TEX_FORMAT_NO_BORDER;
switch (pt->target) {
case PIPE_TEXTURE_CUBE:
txf |= NV34TCL_TX_FORMAT_CUBIC;
txf |= NV30_3D_TEX_FORMAT_CUBIC;
/* fall-through */
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_RECT:
txf |= NV34TCL_TX_FORMAT_DIMS_2D;
txf |= NV30_3D_TEX_FORMAT_DIMS_2D;
break;
case PIPE_TEXTURE_3D:
txf |= NV34TCL_TX_FORMAT_DIMS_3D;
txf |= NV30_3D_TEX_FORMAT_DIMS_3D;
break;
case PIPE_TEXTURE_1D:
txf |= NV34TCL_TX_FORMAT_DIMS_1D;
txf |= NV30_3D_TEX_FORMAT_DIMS_1D;
break;
default:
assert(0);
@@ -102,14 +102,14 @@ nvfx_create_sampler_view(struct pipe_context *pipe,
sv->u.init_fmt = txf;
sv->swizzle = 0
| (tf->src[sv->base.swizzle_r] << NV34TCL_TX_SWIZZLE_S0_Z_SHIFT)
| (tf->src[sv->base.swizzle_g] << NV34TCL_TX_SWIZZLE_S0_Y_SHIFT)
| (tf->src[sv->base.swizzle_b] << NV34TCL_TX_SWIZZLE_S0_X_SHIFT)
| (tf->src[sv->base.swizzle_a] << NV34TCL_TX_SWIZZLE_S0_W_SHIFT)
| (tf->comp[sv->base.swizzle_r] << NV34TCL_TX_SWIZZLE_S1_Z_SHIFT)
| (tf->comp[sv->base.swizzle_g] << NV34TCL_TX_SWIZZLE_S1_Y_SHIFT)
| (tf->comp[sv->base.swizzle_b] << NV34TCL_TX_SWIZZLE_S1_X_SHIFT)
| (tf->comp[sv->base.swizzle_a] << NV34TCL_TX_SWIZZLE_S1_W_SHIFT);
| (tf->src[sv->base.swizzle_r] << NV30_3D_TEX_SWIZZLE_S0_Z__SHIFT)
| (tf->src[sv->base.swizzle_g] << NV30_3D_TEX_SWIZZLE_S0_Y__SHIFT)
| (tf->src[sv->base.swizzle_b] << NV30_3D_TEX_SWIZZLE_S0_X__SHIFT)
| (tf->src[sv->base.swizzle_a] << NV30_3D_TEX_SWIZZLE_S0_W__SHIFT)
| (tf->comp[sv->base.swizzle_r] << NV30_3D_TEX_SWIZZLE_S1_Z__SHIFT)
| (tf->comp[sv->base.swizzle_g] << NV30_3D_TEX_SWIZZLE_S1_Y__SHIFT)
| (tf->comp[sv->base.swizzle_b] << NV30_3D_TEX_SWIZZLE_S1_X__SHIFT)
| (tf->comp[sv->base.swizzle_a] << NV30_3D_TEX_SWIZZLE_S1_W__SHIFT);
sv->filt = tf->sign;
sv->wrap = tf->wrap;
@@ -118,18 +118,18 @@ nvfx_create_sampler_view(struct pipe_context *pipe,
if (pt->target == PIPE_TEXTURE_CUBE)
{
sv->offset = 0;
sv->npot_size = (pt->width0 << NV34TCL_TX_NPOT_SIZE_W_SHIFT) | pt->height0;
sv->npot_size = (pt->width0 << NV30_3D_TEX_NPOT_SIZE_W__SHIFT) | pt->height0;
}
else
{
sv->offset = nvfx_subresource_offset(pt, 0, sv->base.first_level, 0);
sv->npot_size = (u_minify(pt->width0, sv->base.first_level) << NV34TCL_TX_NPOT_SIZE_W_SHIFT) | u_minify(pt->height0, sv->base.first_level);
sv->npot_size = (u_minify(pt->width0, sv->base.first_level) << NV30_3D_TEX_NPOT_SIZE_W__SHIFT) | u_minify(pt->height0, sv->base.first_level);
/* apparently, we need to ignore the t coordinate for 1D textures to fix piglit tex1d-2dborder */
if(pt->target == PIPE_TEXTURE_1D)
{
sv->wrap_mask &=~ NV34TCL_TX_WRAP_T_MASK;
sv->wrap |= NV34TCL_TX_WRAP_T_REPEAT;
sv->wrap_mask &=~ NV30_3D_TEX_WRAP_T__MASK;
sv->wrap |= NV30_3D_TEX_WRAP_T_REPEAT;
}
}
@@ -199,7 +199,7 @@ nvfx_fragtex_validate(struct nvfx_context *nvfx)
} else {
WAIT_RING(chan, 2);
/* this is OK for nv40 too */
OUT_RING(chan, RING_3D(NV34TCL_TX_ENABLE(unit), 1));
OUT_RING(chan, RING_3D(NV30_3D_TEX_ENABLE(unit), 1));
OUT_RING(chan, 0);
nvfx->hw_samplers &= ~(1 << unit);
}
@@ -227,10 +227,10 @@ nvfx_fragtex_relocate(struct nvfx_context *nvfx)
bo = mt->base.bo;
MARK_RING(chan, 3, 3);
OUT_RELOC(chan, bo, RING_3D(NV34TCL_TX_OFFSET(unit), 2), tex_flags | NOUVEAU_BO_DUMMY, 0, 0);
OUT_RELOC(chan, bo, RING_3D(NV30_3D_TEX_OFFSET(unit), 2), tex_flags | NOUVEAU_BO_DUMMY, 0, 0);
OUT_RELOC(chan, bo, 0, tex_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_DUMMY, 0, 0);
OUT_RELOC(chan, bo, nvfx->hw_txf[unit], tex_flags | NOUVEAU_BO_OR | NOUVEAU_BO_DUMMY,
NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1);
NV30_3D_TEX_FORMAT_DMA0, NV30_3D_TEX_FORMAT_DMA1);
}
nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGTEX;
}
@@ -246,32 +246,32 @@ nvfx_init_sampling_functions(struct nvfx_context *nvfx)
nvfx->pipe.sampler_view_destroy = nvfx_sampler_view_destroy;
}
#define NV34TCL_TX_FORMAT_FORMAT_DXT1_RECT NV34TCL_TX_FORMAT_FORMAT_DXT1
#define NV34TCL_TX_FORMAT_FORMAT_DXT3_RECT NV34TCL_TX_FORMAT_FORMAT_DXT3
#define NV34TCL_TX_FORMAT_FORMAT_DXT5_RECT NV34TCL_TX_FORMAT_FORMAT_DXT5
#define NV30_3D_TEX_FORMAT_FORMAT_DXT1_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT1
#define NV30_3D_TEX_FORMAT_FORMAT_DXT3_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT3
#define NV30_3D_TEX_FORMAT_FORMAT_DXT5_RECT NV30_3D_TEX_FORMAT_FORMAT_DXT5
#define NV40TCL_TEX_FORMAT_FORMAT_HILO16 NV40TCL_TEX_FORMAT_FORMAT_A16L16
#define NV40_3D_TEX_FORMAT_FORMAT_HILO16 NV40_3D_TEX_FORMAT_FORMAT_A16L16
#define NV34TCL_TX_FORMAT_FORMAT_RGBA16F 0x00004a00
#define NV34TCL_TX_FORMAT_FORMAT_RGBA16F_RECT NV34TCL_TX_FORMAT_FORMAT_RGBA16F
#define NV34TCL_TX_FORMAT_FORMAT_RGBA32F 0x00004b00
#define NV34TCL_TX_FORMAT_FORMAT_RGBA32F_RECT NV34TCL_TX_FORMAT_FORMAT_RGBA32F
#define NV34TCL_TX_FORMAT_FORMAT_R32F 0x00004c00
#define NV34TCL_TX_FORMAT_FORMAT_R32F_RECT NV34TCL_TX_FORMAT_FORMAT_R32F
#define NV30_3D_TEX_FORMAT_FORMAT_RGBA16F 0x00004a00
#define NV30_3D_TEX_FORMAT_FORMAT_RGBA16F_RECT NV30_3D_TEX_FORMAT_FORMAT_RGBA16F
#define NV30_3D_TEX_FORMAT_FORMAT_RGBA32F 0x00004b00
#define NV30_3D_TEX_FORMAT_FORMAT_RGBA32F_RECT NV30_3D_TEX_FORMAT_FORMAT_RGBA32F
#define NV30_3D_TEX_FORMAT_FORMAT_R32F 0x00004c00
#define NV30_3D_TEX_FORMAT_FORMAT_R32F_RECT NV30_3D_TEX_FORMAT_FORMAT_R32F
// TODO: guess!
#define NV40TCL_TEX_FORMAT_FORMAT_R32F 0x00001c00
#define NV40_3D_TEX_FORMAT_FORMAT_R32F 0x00001c00
#define SRGB 0x00700000
#define __(m,tf,tfc,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sign,wrap) \
[PIPE_FORMAT_##m] = { \
{NV34TCL_TX_FORMAT_FORMAT_##tf, \
NV34TCL_TX_FORMAT_FORMAT_##tfc, \
NV34TCL_TX_FORMAT_FORMAT_##tf##_RECT, \
NV34TCL_TX_FORMAT_FORMAT_##tfc##_RECT, \
NV40TCL_TEX_FORMAT_FORMAT_##tf, \
NV40TCL_TEX_FORMAT_FORMAT_##tfc}, \
{NV30_3D_TEX_FORMAT_FORMAT_##tf, \
NV30_3D_TEX_FORMAT_FORMAT_##tfc, \
NV30_3D_TEX_FORMAT_FORMAT_##tf##_RECT, \
NV30_3D_TEX_FORMAT_FORMAT_##tfc##_RECT, \
NV40_3D_TEX_FORMAT_FORMAT_##tf, \
NV40_3D_TEX_FORMAT_FORMAT_##tfc}, \
sign, wrap, \
{ts0z, ts0y, ts0x, ts0w, 0, 1}, {ts1z, ts1y, ts1x, ts1w, 0, 0} \
}
@@ -293,7 +293,7 @@ nvfx_init_sampling_functions(struct nvfx_context *nvfx)
#define Z 1
#define W 0
#define SNORM ((NV34TCL_TX_FILTER_SIGNED_RED) | (NV34TCL_TX_FILTER_SIGNED_GREEN) | (NV34TCL_TX_FILTER_SIGNED_BLUE) | (NV34TCL_TX_FILTER_SIGNED_ALPHA))
#define SNORM ((NV30_3D_TEX_FILTER_SIGNED_RED) | (NV30_3D_TEX_FILTER_SIGNED_GREEN) | (NV30_3D_TEX_FILTER_SIGNED_BLUE) | (NV30_3D_TEX_FILTER_SIGNED_ALPHA))
#define UNORM 0
struct nvfx_texture_format
src/gallium/drivers/nvfx/nvfx_push.c
+14 -14
View File
@@ -29,7 +29,7 @@ emit_edgeflag(void *priv, boolean enabled)
struct push_context* ctx = priv;
struct nouveau_channel *chan = ctx->chan;
OUT_RING(chan, RING_3D(NV34TCL_EDGEFLAG_ENABLE, 1));
OUT_RING(chan, RING_3D(NV30_3D_EDGEFLAG, 1));
OUT_RING(chan, enabled ? 1 : 0);
}
@@ -44,7 +44,7 @@ emit_vertices_lookup8(void *priv, unsigned start, unsigned count)
unsigned push = MIN2(count, ctx->max_vertices_per_packet);
unsigned length = push * ctx->vertex_length;
OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length));
OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length));
ctx->translate->run_elts8(ctx->translate, elts, push, 0, ctx->chan->cur);
ctx->chan->cur += length;
@@ -64,7 +64,7 @@ emit_vertices_lookup16(void *priv, unsigned start, unsigned count)
unsigned push = MIN2(count, ctx->max_vertices_per_packet);
unsigned length = push * ctx->vertex_length;
OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length));
OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length));
ctx->translate->run_elts16(ctx->translate, elts, push, 0, ctx->chan->cur);
ctx->chan->cur += length;
@@ -84,7 +84,7 @@ emit_vertices_lookup32(void *priv, unsigned start, unsigned count)
unsigned push = MIN2(count, ctx->max_vertices_per_packet);
unsigned length = push * ctx->vertex_length;
OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length));
OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length));
ctx->translate->run_elts(ctx->translate, elts, push, 0, ctx->chan->cur);
ctx->chan->cur += length;
@@ -103,7 +103,7 @@ emit_vertices(void *priv, unsigned start, unsigned count)
unsigned push = MIN2(count, ctx->max_vertices_per_packet);
unsigned length = push * ctx->vertex_length;
OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length));
OUT_RING(ctx->chan, RING_3D_NI(NV30_3D_VERTEX_DATA, length));
ctx->translate->run(ctx->translate, start, push, 0, ctx->chan->cur);
ctx->chan->cur += length;
@@ -141,13 +141,13 @@ emit_ranges(void* priv, unsigned start, unsigned vc, unsigned reg)
static void
emit_ib_ranges(void* priv, unsigned start, unsigned vc)
{
emit_ranges(priv, start, vc, NV34TCL_VB_INDEX_BATCH);
emit_ranges(priv, start, vc, NV30_3D_VB_INDEX_BATCH);
}
static void
emit_vb_ranges(void* priv, unsigned start, unsigned vc)
{
emit_ranges(priv, start, vc, NV34TCL_VB_VERTEX_BATCH);
emit_ranges(priv, start, vc, NV30_3D_VB_VERTEX_BATCH);
}
static INLINE void
@@ -159,7 +159,7 @@ emit_elt8(void* priv, unsigned start, unsigned vc)
int idxbias = ctx->idxbias;
if (vc & 1) {
OUT_RING(chan, RING_3D(NV34TCL_VB_ELEMENT_U32, 1));
OUT_RING(chan, RING_3D(NV30_3D_VB_ELEMENT_U32, 1));
OUT_RING (chan, elts[0]);
elts++; vc--;
}
@@ -168,7 +168,7 @@ emit_elt8(void* priv, unsigned start, unsigned vc)
unsigned i;
unsigned push = MIN2(vc, 2047 * 2);
OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U16, push >> 1));
OUT_RING(chan, RING_3D_NI(NV30_3D_VB_ELEMENT_U16, push >> 1));
for (i = 0; i < push; i+=2)
OUT_RING(chan, ((elts[i+1] + idxbias) << 16) | (elts[i] + idxbias));
@@ -186,7 +186,7 @@ emit_elt16(void* priv, unsigned start, unsigned vc)
int idxbias = ctx->idxbias;
if (vc & 1) {
OUT_RING(chan, RING_3D(NV34TCL_VB_ELEMENT_U32, 1));
OUT_RING(chan, RING_3D(NV30_3D_VB_ELEMENT_U32, 1));
OUT_RING (chan, elts[0]);
elts++; vc--;
}
@@ -195,7 +195,7 @@ emit_elt16(void* priv, unsigned start, unsigned vc)
unsigned i;
unsigned push = MIN2(vc, 2047 * 2);
OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U16, push >> 1));
OUT_RING(chan, RING_3D_NI(NV30_3D_VB_ELEMENT_U16, push >> 1));
for (i = 0; i < push; i+=2)
OUT_RING(chan, ((elts[i+1] + idxbias) << 16) | (elts[i] + idxbias));
@@ -215,7 +215,7 @@ emit_elt32(void* priv, unsigned start, unsigned vc)
while (vc) {
unsigned push = MIN2(vc, 2047);
OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U32, push));
OUT_RING(chan, RING_3D_NI(NV30_3D_VB_ELEMENT_U32, push));
assert(AVAIL_RING(chan) >= push);
if(idxbias)
{
@@ -379,10 +379,10 @@ nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
}
}
OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1));
OUT_RING(chan, hw_mode);
done = util_split_prim_next(&s, max_verts);
OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
OUT_RING(chan, RING_3D(NV30_3D_VERTEX_BEGIN_END, 1));
OUT_RING(chan, 0);
if(done)
src/gallium/drivers/nvfx/nvfx_query.c
+6 -6
View File
@@ -73,9 +73,9 @@ nvfx_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
nouveau_notifier_reset(nvfx->screen->query, q->object->start);
WAIT_RING(chan, 4);
OUT_RING(chan, RING_3D(NV34TCL_QUERY_RESET, 1));
OUT_RING(chan, RING_3D(NV30_3D_QUERY_RESET, 1));
OUT_RING(chan, 1);
OUT_RING(chan, RING_3D(NV34TCL_QUERY_ENABLE, 1));
OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1));
OUT_RING(chan, 1);
q->ready = FALSE;
@@ -93,10 +93,10 @@ nvfx_query_end(struct pipe_context *pipe, struct pipe_query *pq)
assert(nvfx->query == pq);
WAIT_RING(chan, 4);
OUT_RING(chan, RING_3D(NV34TCL_QUERY_GET, 1));
OUT_RING (chan, (0x01 << NV34TCL_QUERY_GET_UNK24_SHIFT) |
((q->object->start * 32) << NV34TCL_QUERY_GET_OFFSET_SHIFT));
OUT_RING(chan, RING_3D(NV34TCL_QUERY_ENABLE, 1));
OUT_RING(chan, RING_3D(NV30_3D_QUERY_GET, 1));
OUT_RING (chan, (0x01 << NV30_3D_QUERY_GET_UNK24__SHIFT) |
((q->object->start * 32) << NV30_3D_QUERY_GET_OFFSET__SHIFT));
OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1));
OUT_RING(chan, 0);
FIRE_RING(chan);
src/gallium/drivers/nvfx/nvfx_screen.c
+29 -29
View File
@@ -4,15 +4,15 @@
#include "util/u_simple_screen.h"
#include "nouveau/nouveau_screen.h"
#include "nouveau/nv_object.xml.h"
#include "nvfx_context.h"
#include "nvfx_screen.h"
#include "nvfx_resource.h"
#include "nvfx_tex.h"
#define NV30TCL_CHIPSET_3X_MASK 0x00000003
#define NV34TCL_CHIPSET_3X_MASK 0x00000010
#define NV35TCL_CHIPSET_3X_MASK 0x000001e0
#define NV30_3D_CHIPSET_3X_MASK 0x00000003
#define NV34_3D_CHIPSET_3X_MASK 0x00000010
#define NV35_3D_CHIPSET_3X_MASK 0x000001e0
#define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
#define NV4X_GRCLASS4497_CHIPSETS 0x00005450
@@ -256,9 +256,9 @@ static void nv30_screen_init(struct nvfx_screen *screen)
/* TODO: perhaps we should do some of this on nv40 too? */
for (i=1; i<8; i++) {
OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1));
OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1));
OUT_RING(chan, 0);
OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i), 1));
OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_VERT(i), 1));
OUT_RING(chan, 0);
}
@@ -294,14 +294,14 @@ static void nv30_screen_init(struct nvfx_screen *screen)
OUT_RING(chan, RING_3D(0x1d88, 1));
OUT_RING(chan, 0x00001200);
OUT_RING(chan, RING_3D(NV34TCL_RC_ENABLE, 1));
OUT_RING(chan, RING_3D(NV30_3D_RC_ENABLE, 1));
OUT_RING(chan, 0);
OUT_RING(chan, RING_3D(NV34TCL_DEPTH_RANGE_NEAR, 2));
OUT_RING(chan, RING_3D(NV30_3D_DEPTH_RANGE_NEAR, 2));
OUT_RING(chan, fui(0.0));
OUT_RING(chan, fui(1.0));
OUT_RING(chan, RING_3D(NV34TCL_MULTISAMPLE_CONTROL, 1));
OUT_RING(chan, RING_3D(NV30_3D_MULTISAMPLE_CONTROL, 1));
OUT_RING(chan, 0xffff0000);
/* enables use of vp rather than fixed-function somehow */
@@ -313,7 +313,7 @@ static void nv40_screen_init(struct nvfx_screen *screen)
{
struct nouveau_channel *chan = screen->base.channel;
OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 2));
OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR2, 2));
OUT_RING(chan, screen->base.channel->vram->handle);
OUT_RING(chan, screen->base.channel->vram->handle);
@@ -343,8 +343,8 @@ static void nv40_screen_init(struct nvfx_screen *screen)
OUT_RING(chan, RING_3D(0x1e94, 1));
OUT_RING(chan, 0x00000001);
OUT_RING(chan, RING_3D(NV40TCL_MIPMAP_ROUNDING, 1));
OUT_RING(chan, NV40TCL_MIPMAP_ROUNDING_DOWN);
OUT_RING(chan, RING_3D(NV40_3D_MIPMAP_ROUNDING, 1));
OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
}
static unsigned
@@ -406,23 +406,23 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
switch (dev->chipset & 0xf0) {
case 0x30:
if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
eng3d_class = 0x0397;
else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
eng3d_class = 0x0697;
else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
eng3d_class = 0x0497;
if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
eng3d_class = NV30_3D;
else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
eng3d_class = NV34_3D;
else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
eng3d_class = NV35_3D;
break;
case 0x40:
if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
eng3d_class = NV40TCL;
eng3d_class = NV40_3D;
else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
eng3d_class = NV44TCL;
eng3d_class = NV44_3D;
screen->is_nv4x = ~0;
break;
case 0x60:
if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
eng3d_class = NV44TCL;
eng3d_class = NV44_3D;
screen->is_nv4x = ~0;
break;
}
@@ -449,7 +449,7 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
/* surely both nv3x and nv44 support index buffers too: find out how and test that */
if(eng3d_class == NV40TCL)
if(eng3d_class == NV40_3D)
screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
@@ -508,25 +508,25 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
/* Static eng3d initialisation */
/* note that we just started using the channel, so we must have space in the pushbuffer */
OUT_RING(chan, RING_3D(NV34TCL_DMA_NOTIFY, 1));
OUT_RING(chan, RING_3D(NV30_3D_DMA_NOTIFY, 1));
OUT_RING(chan, screen->sync->handle);
OUT_RING(chan, RING_3D(NV34TCL_DMA_TEXTURE0, 2));
OUT_RING(chan, RING_3D(NV30_3D_DMA_TEXTURE0, 2));
OUT_RING(chan, chan->vram->handle);
OUT_RING(chan, chan->gart->handle);
OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1));
OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR1, 1));
OUT_RING(chan, chan->vram->handle);
OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 2));
OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR0, 2));
OUT_RING(chan, chan->vram->handle);
OUT_RING(chan, chan->vram->handle);
OUT_RING(chan, RING_3D(NV34TCL_DMA_VTXBUF0, 2));
OUT_RING(chan, RING_3D(NV30_3D_DMA_VTXBUF0, 2));
OUT_RING(chan, chan->vram->handle);
OUT_RING(chan, chan->gart->handle);
OUT_RING(chan, RING_3D(NV34TCL_DMA_FENCE, 2));
OUT_RING(chan, RING_3D(NV30_3D_DMA_FENCE, 2));
OUT_RING(chan, 0);
OUT_RING(chan, screen->query->handle);
OUT_RING(chan, RING_3D(NV34TCL_DMA_IN_MEMORY7, 2));
OUT_RING(chan, RING_3D(NV30_3D_DMA_UNK1AC, 2));
OUT_RING(chan, chan->vram->handle);
OUT_RING(chan, chan->vram->handle);
src/gallium/drivers/nvfx/nvfx_state.c
+34 -34
View File
@@ -20,26 +20,26 @@ nvfx_blend_state_create(struct pipe_context *pipe,
struct nouveau_statebuf_builder sb = sb_init(bso->sb);
if (cso->rt[0].blend_enable) {
sb_method(sb, NV34TCL_BLEND_FUNC_ENABLE, 3);
sb_method(sb, NV30_3D_BLEND_FUNC_ENABLE, 3);
sb_data(sb, 1);
sb_data(sb, (nvgl_blend_func(cso->rt[0].alpha_src_factor) << 16) |
nvgl_blend_func(cso->rt[0].rgb_src_factor));
sb_data(sb, nvgl_blend_func(cso->rt[0].alpha_dst_factor) << 16 |
nvgl_blend_func(cso->rt[0].rgb_dst_factor));
if(nvfx->screen->base.device->chipset < 0x40) {
sb_method(sb, NV34TCL_BLEND_EQUATION, 1);
sb_method(sb, NV30_3D_BLEND_EQUATION, 1);
sb_data(sb, nvgl_blend_eqn(cso->rt[0].rgb_func));
} else {
sb_method(sb, NV40TCL_BLEND_EQUATION, 1);
sb_method(sb, NV40_3D_BLEND_EQUATION, 1);
sb_data(sb, nvgl_blend_eqn(cso->rt[0].alpha_func) << 16 |
nvgl_blend_eqn(cso->rt[0].rgb_func));
}
} else {
sb_method(sb, NV34TCL_BLEND_FUNC_ENABLE, 1);
sb_method(sb, NV30_3D_BLEND_FUNC_ENABLE, 1);
sb_data(sb, 0);
}
sb_method(sb, NV34TCL_COLOR_MASK, 1);
sb_method(sb, NV30_3D_COLOR_MASK, 1);
sb_data(sb, (((cso->rt[0].colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) |
((cso->rt[0].colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) |
((cso->rt[0].colormask & PIPE_MASK_G) ? (0x01 << 8) : 0) |
@@ -48,15 +48,15 @@ nvfx_blend_state_create(struct pipe_context *pipe,
/* TODO: add NV40 MRT color mask */
if (cso->logicop_enable) {
sb_method(sb, NV34TCL_COLOR_LOGIC_OP_ENABLE, 2);
sb_method(sb, NV30_3D_COLOR_LOGIC_OP_ENABLE, 2);
sb_data(sb, 1);
sb_data(sb, nvgl_logicop_func(cso->logicop_func));
} else {
sb_method(sb, NV34TCL_COLOR_LOGIC_OP_ENABLE, 1);
sb_method(sb, NV30_3D_COLOR_LOGIC_OP_ENABLE, 1);
sb_data(sb, 0);
}
sb_method(sb, NV34TCL_DITHER_ENABLE, 1);
sb_method(sb, NV30_3D_DITHER_ENABLE, 1);
sb_data(sb, cso->dither ? 1 : 0);
bso->sb_len = sb_len(sb, bso->sb);
@@ -94,64 +94,64 @@ nvfx_rasterizer_state_create(struct pipe_context *pipe,
* sprite_coord_origin
*/
sb_method(sb, NV34TCL_SHADE_MODEL, 1);
sb_data(sb, cso->flatshade ? NV34TCL_SHADE_MODEL_FLAT :
NV34TCL_SHADE_MODEL_SMOOTH);
sb_method(sb, NV30_3D_SHADE_MODEL, 1);
sb_data(sb, cso->flatshade ? NV30_3D_SHADE_MODEL_FLAT :
NV30_3D_SHADE_MODEL_SMOOTH);
sb_method(sb, NV34TCL_VERTEX_TWO_SIDE_ENABLE, 1);
sb_method(sb, NV30_3D_VERTEX_TWO_SIDE_ENABLE, 1);
sb_data(sb, cso->light_twoside);
sb_method(sb, NV34TCL_LINE_WIDTH, 2);
sb_method(sb, NV30_3D_LINE_WIDTH, 2);
sb_data(sb, (unsigned char)(cso->line_width * 8.0) & 0xff);
sb_data(sb, cso->line_smooth ? 1 : 0);
sb_method(sb, NV34TCL_LINE_STIPPLE_ENABLE, 2);
sb_method(sb, NV30_3D_LINE_STIPPLE_ENABLE, 2);
sb_data(sb, cso->line_stipple_enable ? 1 : 0);
sb_data(sb, (cso->line_stipple_pattern << 16) |
cso->line_stipple_factor);
sb_method(sb, NV34TCL_POINT_SIZE, 1);
sb_method(sb, NV30_3D_POINT_SIZE, 1);
sb_data(sb, fui(cso->point_size));
sb_method(sb, NV34TCL_POLYGON_MODE_FRONT, 6);
sb_method(sb, NV30_3D_POLYGON_MODE_FRONT, 6);
sb_data(sb, nvgl_polygon_mode(cso->fill_front));
sb_data(sb, nvgl_polygon_mode(cso->fill_back));
switch (cso->cull_face) {
case PIPE_FACE_FRONT:
sb_data(sb, NV34TCL_CULL_FACE_FRONT);
sb_data(sb, NV30_3D_CULL_FACE_FRONT);
break;
case PIPE_FACE_BACK:
sb_data(sb, NV34TCL_CULL_FACE_BACK);
sb_data(sb, NV30_3D_CULL_FACE_BACK);
break;
case PIPE_FACE_FRONT_AND_BACK:
sb_data(sb, NV34TCL_CULL_FACE_FRONT_AND_BACK);
sb_data(sb, NV30_3D_CULL_FACE_FRONT_AND_BACK);
break;
default:
sb_data(sb, NV34TCL_CULL_FACE_BACK);
sb_data(sb, NV30_3D_CULL_FACE_BACK);
break;
}
if (cso->front_ccw) {
sb_data(sb, NV34TCL_FRONT_FACE_CCW);
sb_data(sb, NV30_3D_FRONT_FACE_CCW);
} else {
sb_data(sb, NV34TCL_FRONT_FACE_CW);
sb_data(sb, NV30_3D_FRONT_FACE_CW);
}
sb_data(sb, cso->poly_smooth ? 1 : 0);
sb_data(sb, (cso->cull_face != PIPE_FACE_NONE) ? 1 : 0);
sb_method(sb, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
sb_method(sb, NV30_3D_POLYGON_STIPPLE_ENABLE, 1);
sb_data(sb, cso->poly_stipple_enable ? 1 : 0);
sb_method(sb, NV34TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
sb_method(sb, NV30_3D_POLYGON_OFFSET_POINT_ENABLE, 3);
sb_data(sb, cso->offset_point);
sb_data(sb, cso->offset_line);
sb_data(sb, cso->offset_tri);
if (cso->offset_point || cso->offset_line || cso->offset_tri) {
sb_method(sb, NV34TCL_POLYGON_OFFSET_FACTOR, 2);
sb_method(sb, NV30_3D_POLYGON_OFFSET_FACTOR, 2);
sb_data(sb, fui(cso->offset_scale));
sb_data(sb, fui(cso->offset_units * 2));
}
sb_method(sb, NV34TCL_FLATSHADE_FIRST, 1);
sb_method(sb, NV30_3D_FLATSHADE_FIRST, 1);
sb_data(sb, cso->flatshade_first);
rsso->pipe = *cso;
@@ -201,41 +201,41 @@ nvfx_depth_stencil_alpha_state_create(struct pipe_context *pipe,
struct nvfx_zsa_state *zsaso = CALLOC(1, sizeof(*zsaso));
struct nouveau_statebuf_builder sb = sb_init(zsaso->sb);
sb_method(sb, NV34TCL_DEPTH_FUNC, 1);
sb_method(sb, NV30_3D_DEPTH_FUNC, 1);
sb_data (sb, nvgl_comparison_op(cso->depth.func));
sb_method(sb, NV34TCL_ALPHA_FUNC_ENABLE, 3);
sb_method(sb, NV30_3D_ALPHA_FUNC_ENABLE, 3);
sb_data (sb, cso->alpha.enabled ? 1 : 0);
sb_data (sb, nvgl_comparison_op(cso->alpha.func));
sb_data (sb, float_to_ubyte(cso->alpha.ref_value));
if (cso->stencil[0].enabled) {
sb_method(sb, NV34TCL_STENCIL_FRONT_ENABLE, 3);
sb_method(sb, NV30_3D_STENCIL_ENABLE(0), 3);
sb_data (sb, cso->stencil[0].enabled ? 1 : 0);
sb_data (sb, cso->stencil[0].writemask);
sb_data (sb, nvgl_comparison_op(cso->stencil[0].func));
sb_method(sb, NV34TCL_STENCIL_FRONT_FUNC_MASK, 4);
sb_method(sb, NV30_3D_STENCIL_FUNC_MASK(0), 4);
sb_data (sb, cso->stencil[0].valuemask);
sb_data (sb, nvgl_stencil_op(cso->stencil[0].fail_op));
sb_data (sb, nvgl_stencil_op(cso->stencil[0].zfail_op));
sb_data (sb, nvgl_stencil_op(cso->stencil[0].zpass_op));
} else {
sb_method(sb, NV34TCL_STENCIL_FRONT_ENABLE, 1);
sb_method(sb, NV30_3D_STENCIL_ENABLE(0), 1);
sb_data (sb, 0);
}
if (cso->stencil[1].enabled) {
sb_method(sb, NV34TCL_STENCIL_BACK_ENABLE, 3);
sb_method(sb, NV30_3D_STENCIL_ENABLE(1), 3);
sb_data (sb, cso->stencil[1].enabled ? 1 : 0);
sb_data (sb, cso->stencil[1].writemask);
sb_data (sb, nvgl_comparison_op(cso->stencil[1].func));
sb_method(sb, NV34TCL_STENCIL_BACK_FUNC_MASK, 4);
sb_method(sb, NV30_3D_STENCIL_FUNC_MASK(1), 4);
sb_data (sb, cso->stencil[1].valuemask);
sb_data (sb, nvgl_stencil_op(cso->stencil[1].fail_op));
sb_data (sb, nvgl_stencil_op(cso->stencil[1].zfail_op));
sb_data (sb, nvgl_stencil_op(cso->stencil[1].zpass_op));
} else {
sb_method(sb, NV34TCL_STENCIL_BACK_ENABLE, 1);
sb_method(sb, NV30_3D_STENCIL_ENABLE(1), 1);
sb_data (sb, 0);
}
src/gallium/drivers/nvfx/nvfx_state_emit.c
+28 -28
View File
@@ -11,7 +11,7 @@ nvfx_state_viewport_validate(struct nvfx_context *nvfx)
WAIT_RING(chan, 11);
if(nvfx->render_mode == HW) {
OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_TRANSLATE_X, 8));
OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_TRANSLATE_X, 8));
OUT_RINGf(chan, vpt->translate[0]);
OUT_RINGf(chan, vpt->translate[1]);
OUT_RINGf(chan, vpt->translate[2]);
@@ -23,7 +23,7 @@ nvfx_state_viewport_validate(struct nvfx_context *nvfx)
OUT_RING(chan, RING_3D(0x1d78, 1));
OUT_RING(chan, 1);
} else {
OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_TRANSLATE_X, 8));
OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_TRANSLATE_X, 8));
OUT_RINGf(chan, 0.0f);
OUT_RINGf(chan, 0.0f);
OUT_RINGf(chan, 0.0f);
@@ -49,7 +49,7 @@ nvfx_state_scissor_validate(struct nvfx_context *nvfx)
nvfx->state.scissor_enabled = rast->scissor;
WAIT_RING(chan, 3);
OUT_RING(chan, RING_3D(NV34TCL_SCISSOR_HORIZ, 2));
OUT_RING(chan, RING_3D(NV30_3D_SCISSOR_HORIZ, 2));
if (nvfx->state.scissor_enabled) {
OUT_RING(chan, ((s->maxx - s->minx) << 16) | s->minx);
OUT_RING(chan, ((s->maxy - s->miny) << 16) | s->miny);
@@ -66,9 +66,9 @@ nvfx_state_sr_validate(struct nvfx_context *nvfx)
struct pipe_stencil_ref *sr = &nvfx->stencil_ref;
WAIT_RING(chan, 4);
OUT_RING(chan, RING_3D(NV34TCL_STENCIL_FRONT_FUNC_REF, 1));
OUT_RING(chan, RING_3D(NV30_3D_STENCIL_FUNC_REF(0), 1));
OUT_RING(chan, sr->ref_value[0]);
OUT_RING(chan, RING_3D(NV34TCL_STENCIL_BACK_FUNC_REF, 1));
OUT_RING(chan, RING_3D(NV30_3D_STENCIL_FUNC_REF(1), 1));
OUT_RING(chan, sr->ref_value[1]);
}
@@ -79,7 +79,7 @@ nvfx_state_blend_colour_validate(struct nvfx_context *nvfx)
struct pipe_blend_color *bcol = &nvfx->blend_colour;
WAIT_RING(chan, 2);
OUT_RING(chan, RING_3D(NV34TCL_BLEND_COLOR, 1));
OUT_RING(chan, RING_3D(NV30_3D_BLEND_COLOR, 1));
OUT_RING(chan, ((float_to_ubyte(bcol->color[3]) << 24) |
(float_to_ubyte(bcol->color[0]) << 16) |
(float_to_ubyte(bcol->color[1]) << 8) |
@@ -92,7 +92,7 @@ nvfx_state_stipple_validate(struct nvfx_context *nvfx)
struct nouveau_channel *chan = nvfx->screen->base.channel;
WAIT_RING(chan, 33);
OUT_RING(chan, RING_3D(NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32));
OUT_RING(chan, RING_3D(NV30_3D_POLYGON_STIPPLE_PATTERN(0), 32));
OUT_RINGp(chan, nvfx->stipple, 32);
}
@@ -101,11 +101,11 @@ nvfx_coord_conventions_validate(struct nvfx_context* nvfx)
{
struct nouveau_channel* chan = nvfx->screen->base.channel;
unsigned value = nvfx->hw_fragprog->coord_conventions;
if(value & NV34TCL_COORD_CONVENTIONS_ORIGIN_INVERTED)
value |= nvfx->framebuffer.height << NV34TCL_COORD_CONVENTIONS_HEIGHT_SHIFT;
if(value & NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED)
value |= nvfx->framebuffer.height << NV30_3D_COORD_CONVENTIONS_HEIGHT__SHIFT;
WAIT_RING(chan, 2);
OUT_RING(chan, RING_3D(NV34TCL_COORD_CONVENTIONS, 1));
OUT_RING(chan, RING_3D(NV30_3D_COORD_CONVENTIONS, 1));
OUT_RING(chan, value);
}
@@ -116,27 +116,27 @@ nvfx_ucp_validate(struct nvfx_context* nvfx)
unsigned enables[7] =
{
0,
NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0,
NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1,
NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2,
NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3,
NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4,
NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5,
NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0,
NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1,
NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2,
NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3,
NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE4,
NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE0 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE1 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE2 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE3 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE4 | NV30_3D_VP_CLIP_PLANES_ENABLE_PLANE5,
};
if(!nvfx->use_vp_clipping)
{
WAIT_RING(chan, 2);
OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1));
OUT_RING(chan, RING_3D(NV30_3D_VP_CLIP_PLANES_ENABLE, 1));
OUT_RING(chan, 0);
WAIT_RING(chan, 6 * 4 + 1);
OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANE_A(0), nvfx->clip.nr * 4));
OUT_RING(chan, RING_3D(NV30_3D_VP_CLIP_PLANE(0, 0), nvfx->clip.nr * 4));
OUT_RINGp(chan, &nvfx->clip.ucp[0][0], nvfx->clip.nr * 4);
}
WAIT_RING(chan, 2);
OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1));
OUT_RING(chan, RING_3D(NV30_3D_VP_CLIP_PLANES_ENABLE, 1));
OUT_RING(chan, enables[nvfx->clip.nr]);
}
@@ -155,17 +155,17 @@ nvfx_vertprog_ucp_validate(struct nvfx_context* nvfx)
if(vp->clip_nr >= 0)
{
idx = vp->nr_insns - 7 + vp->clip_nr;
OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_FROM_ID, 1));
OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_FROM_ID, 1));
OUT_RING(chan, vp->exec->start + idx);
OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_INST(0), 4));
OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_INST(0), 4));
OUT_RINGp (chan, vp->insns[idx].data, 4);
}
/* set last instruction bit */
idx = vp->nr_insns - 7 + nvfx->clip.nr;
OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_FROM_ID, 1));
OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_FROM_ID, 1));
OUT_RING(chan, vp->exec->start + idx);
OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_INST(0), 4));
OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_INST(0), 4));
OUT_RINGp(chan, vp->insns[idx].data, 3);
OUT_RING(chan, vp->insns[idx].data[3] | 1);
vp->clip_nr = nvfx->clip.nr;
@@ -175,7 +175,7 @@ nvfx_vertprog_ucp_validate(struct nvfx_context* nvfx)
WAIT_RING(chan, 6 * 6);
for(i = 0; i < nvfx->clip.nr; ++i)
{
OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_CONST_ID, 5));
OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5));
OUT_RING(chan, vp->data->start + i);
OUT_RINGp (chan, nvfx->clip.ucp[i], 4);
}
@@ -288,7 +288,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
if(vp_output != nvfx->hw_vp_output)
{
WAIT_RING(chan, 2);
OUT_RING(chan, RING_3D(NV40TCL_VP_RESULT_EN, 1));
OUT_RING(chan, RING_3D(NV40_3D_VP_RESULT_EN, 1));
OUT_RING(chan, vp_output);
nvfx->hw_vp_output = vp_output;
}
@@ -321,7 +321,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
if(dirty & NVFX_NEW_ZSA || (new_fb_mode >= 0))
{
WAIT_RING(chan, 3);
OUT_RING(chan, RING_3D(NV34TCL_DEPTH_WRITE_ENABLE, 2));
OUT_RING(chan, RING_3D(NV30_3D_DEPTH_WRITE_ENABLE, 2));
OUT_RING(chan, nvfx->framebuffer.zsbuf && nvfx->zsa->pipe.depth.writemask);
OUT_RING(chan, nvfx->framebuffer.zsbuf && nvfx->zsa->pipe.depth.enabled);
}
@@ -335,9 +335,9 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
if(nvfx->is_nv4x)
{
WAIT_RING(chan, 4);
OUT_RING(chan, RING_3D(NV40TCL_TEX_CACHE_CTL, 1));
OUT_RING(chan, RING_3D(NV40_3D_TEX_CACHE_CTL, 1));
OUT_RING(chan, 2);
OUT_RING(chan, RING_3D(NV40TCL_TEX_CACHE_CTL, 1));
OUT_RING(chan, RING_3D(NV40_3D_TEX_CACHE_CTL, 1));
OUT_RING(chan, 1);
}
}
src/gallium/drivers/nvfx/nvfx_state_fb.c
+48 -48
View File
@@ -102,10 +102,10 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result)
unsigned w = fb->width;
unsigned h = fb->height;
rt_enable = (NV34TCL_RT_ENABLE_COLOR0 << fb->nr_cbufs) - 1;
if (rt_enable & (NV34TCL_RT_ENABLE_COLOR1 |
NV40TCL_RT_ENABLE_COLOR2 | NV40TCL_RT_ENABLE_COLOR3))
rt_enable |= NV34TCL_RT_ENABLE_MRT;
rt_enable = (NV30_3D_RT_ENABLE_COLOR0 << fb->nr_cbufs) - 1;
if (rt_enable & (NV30_3D_RT_ENABLE_COLOR1 |
NV40_3D_RT_ENABLE_COLOR2 | NV40_3D_RT_ENABLE_COLOR3))
rt_enable |= NV30_3D_RT_ENABLE_MRT;
nvfx->state.render_temps = 0;
@@ -125,63 +125,63 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result)
if (prepare_result) {
assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1)));
rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED |
(util_logbase2(fb->width) << NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT) |
(util_logbase2(fb->height) << NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT);
rt_format = NV30_3D_RT_FORMAT_TYPE_SWIZZLED |
(util_logbase2(fb->width) << NV30_3D_RT_FORMAT_LOG2_WIDTH__SHIFT) |
(util_logbase2(fb->height) << NV30_3D_RT_FORMAT_LOG2_HEIGHT__SHIFT);
} else
rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
rt_format = NV30_3D_RT_FORMAT_TYPE_LINEAR;
if(fb->nr_cbufs > 0) {
switch (fb->cbufs[0]->format) {
case PIPE_FORMAT_B8G8R8X8_UNORM:
rt_format |= NV34TCL_RT_FORMAT_COLOR_X8R8G8B8;
rt_format |= NV30_3D_RT_FORMAT_COLOR_X8R8G8B8;
break;
case PIPE_FORMAT_B8G8R8A8_UNORM:
case 0:
rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8;
rt_format |= NV30_3D_RT_FORMAT_COLOR_A8R8G8B8;
break;
case PIPE_FORMAT_B5G6R5_UNORM:
rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5;
rt_format |= NV30_3D_RT_FORMAT_COLOR_R5G6B5;
break;
case PIPE_FORMAT_R32G32B32A32_FLOAT:
rt_format |= NV34TCL_RT_FORMAT_COLOR_A32B32G32R32_FLOAT;
rt_format |= NV30_3D_RT_FORMAT_COLOR_A32B32G32R32_FLOAT;
break;
case PIPE_FORMAT_R16G16B16A16_FLOAT:
rt_format |= NV34TCL_RT_FORMAT_COLOR_A16B16G16R16_FLOAT;
rt_format |= NV30_3D_RT_FORMAT_COLOR_A16B16G16R16_FLOAT;
break;
default:
assert(0);
}
} else if(fb->zsbuf && util_format_get_blocksize(fb->zsbuf->format) == 2)
rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5;
rt_format |= NV30_3D_RT_FORMAT_COLOR_R5G6B5;
else
rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8;
rt_format |= NV30_3D_RT_FORMAT_COLOR_A8R8G8B8;
if(fb->zsbuf) {
switch (fb->zsbuf->format) {
case PIPE_FORMAT_Z16_UNORM:
rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16;
rt_format |= NV30_3D_RT_FORMAT_ZETA_Z16;
break;
case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
case PIPE_FORMAT_X8Z24_UNORM:
case 0:
rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8;
rt_format |= NV30_3D_RT_FORMAT_ZETA_Z24S8;
break;
default:
assert(0);
}
} else if(fb->nr_cbufs && util_format_get_blocksize(fb->cbufs[0]->format) == 2)
rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16;
rt_format |= NV30_3D_RT_FORMAT_ZETA_Z16;
else
rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8;
rt_format |= NV30_3D_RT_FORMAT_ZETA_Z24S8;
MARK_RING(chan, 42, 10);
if ((rt_enable & NV34TCL_RT_ENABLE_COLOR0) || fb->zsbuf) {
if ((rt_enable & NV30_3D_RT_ENABLE_COLOR0) || fb->zsbuf) {
struct nvfx_render_target *rt0 = &nvfx->hw_rt[0];
uint32_t pitch;
if(!(rt_enable & NV34TCL_RT_ENABLE_COLOR0))
if(!(rt_enable & NV30_3D_RT_ENABLE_COLOR0))
rt0 = &nvfx->hw_zeta;
pitch = rt0->pitch;
@@ -196,23 +196,23 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result)
//printf("rendering to bo %p [%i] at offset %i with pitch %i\n", rt0->bo, rt0->bo->handle, rt0->offset, pitch);
OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 1));
OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR0, 1));
OUT_RELOC(chan, rt0->bo, 0,
rt_flags | NOUVEAU_BO_OR,
chan->vram->handle, chan->gart->handle);
OUT_RING(chan, RING_3D(NV34TCL_COLOR0_PITCH, 2));
OUT_RING(chan, RING_3D(NV30_3D_COLOR0_PITCH, 2));
OUT_RING(chan, pitch);
OUT_RELOC(chan, rt0->bo,
rt0->offset, rt_flags | NOUVEAU_BO_LOW,
0, 0);
}
if (rt_enable & NV34TCL_RT_ENABLE_COLOR1) {
OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1));
if (rt_enable & NV30_3D_RT_ENABLE_COLOR1) {
OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR1, 1));
OUT_RELOC(chan, nvfx->hw_rt[1].bo, 0,
rt_flags | NOUVEAU_BO_OR,
chan->vram->handle, chan->gart->handle);
OUT_RING(chan, RING_3D(NV34TCL_COLOR1_OFFSET, 2));
OUT_RING(chan, RING_3D(NV30_3D_COLOR1_OFFSET, 2));
OUT_RELOC(chan, nvfx->hw_rt[1].bo,
nvfx->hw_rt[1].offset, rt_flags | NOUVEAU_BO_LOW,
0, 0);
@@ -221,69 +221,69 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result)
if(nvfx->is_nv4x)
{
if (rt_enable & NV40TCL_RT_ENABLE_COLOR2) {
OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 1));
if (rt_enable & NV40_3D_RT_ENABLE_COLOR2) {
OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR2, 1));
OUT_RELOC(chan, nvfx->hw_rt[2].bo, 0,
rt_flags | NOUVEAU_BO_OR,
chan->vram->handle, chan->gart->handle);
OUT_RING(chan, RING_3D(NV40TCL_COLOR2_OFFSET, 1));
OUT_RING(chan, RING_3D(NV40_3D_COLOR2_OFFSET, 1));
OUT_RELOC(chan, nvfx->hw_rt[2].bo,
nvfx->hw_rt[2].offset, rt_flags | NOUVEAU_BO_LOW,
0, 0);
OUT_RING(chan, RING_3D(NV40TCL_COLOR2_PITCH, 1));
OUT_RING(chan, RING_3D(NV40_3D_COLOR2_PITCH, 1));
OUT_RING(chan, nvfx->hw_rt[2].pitch);
}
if (rt_enable & NV40TCL_RT_ENABLE_COLOR3) {
OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR3, 1));
if (rt_enable & NV40_3D_RT_ENABLE_COLOR3) {
OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR3, 1));
OUT_RELOC(chan, nvfx->hw_rt[3].bo, 0,
rt_flags | NOUVEAU_BO_OR,
chan->vram->handle, chan->gart->handle);
OUT_RING(chan, RING_3D(NV40TCL_COLOR3_OFFSET, 1));
OUT_RING(chan, RING_3D(NV40_3D_COLOR3_OFFSET, 1));
OUT_RELOC(chan, nvfx->hw_rt[3].bo,
nvfx->hw_rt[3].offset, rt_flags | NOUVEAU_BO_LOW,
0, 0);
OUT_RING(chan, RING_3D(NV40TCL_COLOR3_PITCH, 1));
OUT_RING(chan, RING_3D(NV40_3D_COLOR3_PITCH, 1));
OUT_RING(chan, nvfx->hw_rt[3].pitch);
}
}
if (fb->zsbuf) {
OUT_RING(chan, RING_3D(NV34TCL_DMA_ZETA, 1));
OUT_RING(chan, RING_3D(NV30_3D_DMA_ZETA, 1));
OUT_RELOC(chan, nvfx->hw_zeta.bo, 0,
rt_flags | NOUVEAU_BO_OR,
chan->vram->handle, chan->gart->handle);
OUT_RING(chan, RING_3D(NV34TCL_ZETA_OFFSET, 1));
OUT_RING(chan, RING_3D(NV30_3D_ZETA_OFFSET, 1));
/* TODO: reverse engineer LMA */
OUT_RELOC(chan, nvfx->hw_zeta.bo,
nvfx->hw_zeta.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0);
if(nvfx->is_nv4x) {
OUT_RING(chan, RING_3D(NV40TCL_ZETA_PITCH, 1));
OUT_RING(chan, RING_3D(NV40_3D_ZETA_PITCH, 1));
OUT_RING(chan, nvfx->hw_zeta.pitch);
}
}
else if(nvfx->is_nv4x) {
OUT_RING(chan, RING_3D(NV40TCL_ZETA_PITCH, 1));
OUT_RING(chan, RING_3D(NV40_3D_ZETA_PITCH, 1));
OUT_RING(chan, 64);
}
OUT_RING(chan, RING_3D(NV34TCL_RT_ENABLE, 1));
OUT_RING(chan, RING_3D(NV30_3D_RT_ENABLE, 1));
OUT_RING(chan, rt_enable);
OUT_RING(chan, RING_3D(NV34TCL_RT_HORIZ, 3));
OUT_RING(chan, RING_3D(NV30_3D_RT_HORIZ, 3));
OUT_RING(chan, (w << 16) | 0);
OUT_RING(chan, (h << 16) | 0);
OUT_RING(chan, rt_format);
OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_HORIZ, 2));
OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_HORIZ, 2));
OUT_RING(chan, (w << 16) | 0);
OUT_RING(chan, (h << 16) | 0);
OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2));
OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_HORIZ(0), 2));
OUT_RING(chan, ((w - 1) << 16) | 0);
OUT_RING(chan, ((h - 1) << 16) | 0);
if(!nvfx->is_nv4x) {
/* Wonder why this is needed, context should all be set to zero on init */
/* TODO: we can most likely remove this, after putting it in context init */
OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_TX_ORIGIN, 1));
OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_TX_ORIGIN, 1));
OUT_RING(chan, 0);
}
nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAMEBUFFER;
@@ -299,22 +299,22 @@ nvfx_framebuffer_relocate(struct nvfx_context *nvfx)
#define DO_(var, pfx, name) \
if(var.bo) { \
OUT_RELOC(chan, var.bo, RING_3D(pfx##TCL_DMA_##name, 1), rt_flags, 0, 0); \
OUT_RELOC(chan, var.bo, RING_3D(pfx##_3D_DMA_##name, 1), rt_flags, 0, 0); \
OUT_RELOC(chan, var.bo, 0, \
rt_flags | NOUVEAU_BO_OR, \
chan->vram->handle, chan->gart->handle); \
OUT_RELOC(chan, var.bo, RING_3D(pfx##TCL_##name##_OFFSET, 1), rt_flags, 0, 0); \
OUT_RELOC(chan, var.bo, RING_3D(pfx##_3D_##name##_OFFSET, 1), rt_flags, 0, 0); \
OUT_RELOC(chan, var.bo, \
var.offset, rt_flags | NOUVEAU_BO_LOW, \
0, 0); \
}
#define DO(pfx, num) DO_(nvfx->hw_rt[num], pfx, COLOR##num)
DO(NV34, 0);
DO(NV34, 1);
DO(NV30, 0);
DO(NV30, 1);
DO(NV40, 2);
DO(NV40, 3);
DO_(nvfx->hw_zeta, NV34, ZETA);
DO_(nvfx->hw_zeta, NV30, ZETA);
nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAMEBUFFER;
}
src/gallium/drivers/nvfx/nvfx_surface.c
+2 -2
View File
@@ -167,7 +167,7 @@ nvfx_get_blitter(struct pipe_context* pipe, int copy)
{
struct nouveau_channel* chan = nvfx->screen->base.channel;
WAIT_RING(chan, 2);
OUT_RING(chan, RING_3D(NV34TCL_QUERY_ENABLE, 1));
OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1));
OUT_RING(chan, 0);
}
@@ -208,7 +208,7 @@ nvfx_put_blitter(struct pipe_context* pipe, struct blitter_context* blitter)
{
struct nouveau_channel* chan = nvfx->screen->base.channel;
WAIT_RING(chan, 2);
OUT_RING(chan, RING_3D(NV34TCL_QUERY_ENABLE, 1));
OUT_RING(chan, RING_3D(NV30_3D_QUERY_ENABLE, 1));
OUT_RING(chan, 1);
}
}
src/gallium/drivers/nvfx/nvfx_tex.h
+27 -27
View File
@@ -4,7 +4,7 @@
#include "util/u_math.h"
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include <nouveau/nouveau_class.h>
static inline unsigned
nvfx_tex_wrap_mode(unsigned wrap) {
@@ -12,36 +12,36 @@ nvfx_tex_wrap_mode(unsigned wrap) {
switch (wrap) {
case PIPE_TEX_WRAP_REPEAT:
ret = NV34TCL_TX_WRAP_S_REPEAT;
ret = NV30_3D_TEX_WRAP_S_REPEAT;
break;
case PIPE_TEX_WRAP_MIRROR_REPEAT:
ret = NV34TCL_TX_WRAP_S_MIRRORED_REPEAT;
ret = NV30_3D_TEX_WRAP_S_MIRRORED_REPEAT;
break;
case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
ret = NV34TCL_TX_WRAP_S_CLAMP_TO_EDGE;
ret = NV30_3D_TEX_WRAP_S_CLAMP_TO_EDGE;
break;
case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
ret = NV34TCL_TX_WRAP_S_CLAMP_TO_BORDER;
ret = NV30_3D_TEX_WRAP_S_CLAMP_TO_BORDER;
break;
case PIPE_TEX_WRAP_CLAMP:
ret = NV34TCL_TX_WRAP_S_CLAMP;
ret = NV30_3D_TEX_WRAP_S_CLAMP;
break;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
break;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
break;
case PIPE_TEX_WRAP_MIRROR_CLAMP:
ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP;
ret = NV40_3D_TEX_WRAP_S_MIRROR_CLAMP;
break;
default:
assert(0);
ret = NV34TCL_TX_WRAP_S_REPEAT;
ret = NV30_3D_TEX_WRAP_S_REPEAT;
break;
}
return ret >> NV34TCL_TX_WRAP_S_SHIFT;
return ret >> NV30_3D_TEX_WRAP_S__SHIFT;
}
static inline unsigned
@@ -49,21 +49,21 @@ nvfx_tex_wrap_compare_mode(unsigned func)
{
switch (func) {
case PIPE_FUNC_NEVER:
return NV34TCL_TX_WRAP_RCOMP_NEVER;
return NV30_3D_TEX_WRAP_RCOMP_NEVER;
case PIPE_FUNC_GREATER:
return NV34TCL_TX_WRAP_RCOMP_GREATER;
return NV30_3D_TEX_WRAP_RCOMP_GREATER;
case PIPE_FUNC_EQUAL:
return NV34TCL_TX_WRAP_RCOMP_EQUAL;
return NV30_3D_TEX_WRAP_RCOMP_EQUAL;
case PIPE_FUNC_GEQUAL:
return NV34TCL_TX_WRAP_RCOMP_GEQUAL;
return NV30_3D_TEX_WRAP_RCOMP_GEQUAL;
case PIPE_FUNC_LESS:
return NV34TCL_TX_WRAP_RCOMP_LESS;
return NV30_3D_TEX_WRAP_RCOMP_LESS;
case PIPE_FUNC_NOTEQUAL:
return NV34TCL_TX_WRAP_RCOMP_NOTEQUAL;
return NV30_3D_TEX_WRAP_RCOMP_NOTEQUAL;
case PIPE_FUNC_LEQUAL:
return NV34TCL_TX_WRAP_RCOMP_LEQUAL;
return NV30_3D_TEX_WRAP_RCOMP_LEQUAL;
case PIPE_FUNC_ALWAYS:
return NV34TCL_TX_WRAP_RCOMP_ALWAYS;
return NV30_3D_TEX_WRAP_RCOMP_ALWAYS;
default:
assert(0);
return 0;
@@ -75,11 +75,11 @@ static inline unsigned nvfx_tex_filter(const struct pipe_sampler_state* cso)
unsigned filter = 0;
switch (cso->mag_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
filter |= NV34TCL_TX_FILTER_MAGNIFY_LINEAR;
filter |= NV30_3D_TEX_FILTER_MAG_LINEAR;
break;
case PIPE_TEX_FILTER_NEAREST:
default:
filter |= NV34TCL_TX_FILTER_MAGNIFY_NEAREST;
filter |= NV30_3D_TEX_FILTER_MAG_NEAREST;
break;
}
@@ -87,14 +87,14 @@ static inline unsigned nvfx_tex_filter(const struct pipe_sampler_state* cso)
case PIPE_TEX_FILTER_LINEAR:
switch (cso->min_mip_filter) {
case PIPE_TEX_MIPFILTER_NEAREST:
filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST;
filter |= NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST;
break;
case PIPE_TEX_MIPFILTER_LINEAR:
filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR;
filter |= NV30_3D_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR;
break;
case PIPE_TEX_MIPFILTER_NONE:
default:
filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR;
filter |= NV30_3D_TEX_FILTER_MIN_LINEAR;
break;
}
break;
@@ -102,14 +102,14 @@ static inline unsigned nvfx_tex_filter(const struct pipe_sampler_state* cso)
default:
switch (cso->min_mip_filter) {
case PIPE_TEX_MIPFILTER_NEAREST:
filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST;
filter |= NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST;
break;
case PIPE_TEX_MIPFILTER_LINEAR:
filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR;
filter |= NV30_3D_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR;
break;
case PIPE_TEX_MIPFILTER_NONE:
default:
filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST;
filter |= NV30_3D_TEX_FILTER_MIN_NEAREST;
break;
}
break;
src/gallium/drivers/nvfx/nvfx_vbo.c
+40 -40
View File
@@ -9,7 +9,7 @@
#include "nvfx_resource.h"
#include "nouveau/nouveau_channel.h"
#include "nouveau/nouveau_class.h"
#include "nouveau/nouveau_pushbuf.h"
static inline unsigned
@@ -266,7 +266,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx)
}
OUT_RING(chan, RING_3D(NV34TCL_VTXFMT(0), elements));
OUT_RING(chan, RING_3D(NV30_3D_VTXFMT(0), elements));
if(nvfx->use_vertex_buffers)
{
unsigned idx = 0;
@@ -281,7 +281,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx)
idx = ve->idx;
}
OUT_RING(chan, nvfx->vtxelt->vtxfmt[idx] | (vb->stride << NV34TCL_VTXFMT_STRIDE_SHIFT));
OUT_RING(chan, nvfx->vtxelt->vtxfmt[idx] | (vb->stride << NV30_3D_VTXFMT_STRIDE__SHIFT));
++idx;
}
if(idx != nvfx->vtxelt->num_elements)
@@ -291,7 +291,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx)
OUT_RINGp(chan, nvfx->vtxelt->vtxfmt, nvfx->vtxelt->num_elements);
for(i = nvfx->vtxelt->num_elements; i < elements; ++i)
OUT_RING(chan, NV34TCL_VTXFMT_TYPE_32_FLOAT);
OUT_RING(chan, NV30_3D_VTXFMT_TYPE_V32_FLOAT);
if(nvfx->is_nv4x) {
unsigned i;
@@ -302,7 +302,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx)
}
}
OUT_RING(chan, RING_3D(NV34TCL_VTXBUF_ADDRESS(0), elements));
OUT_RING(chan, RING_3D(NV30_3D_VTXBUF(0), elements));
if(nvfx->use_vertex_buffers)
{
unsigned idx = 0;
@@ -317,7 +317,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx)
OUT_RELOC(chan, bo,
vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride,
vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
0, NV34TCL_VTXBUF_ADDRESS_DMA1);
0, NV30_3D_VTXBUF_DMA1);
++idx;
}
@@ -350,11 +350,11 @@ nvfx_vbo_swtnl_validate(struct nvfx_context *nvfx)
WAIT_RING(chan, (1 + 6 + 1 + 2) + elements * 2);
OUT_RING(chan, RING_3D(NV34TCL_VTXFMT(0), elements));
OUT_RING(chan, RING_3D(NV30_3D_VTXFMT(0), elements));
for(unsigned i = 0; i < num_outputs; ++i)
OUT_RING(chan, (4 << NV34TCL_VTXFMT_SIZE_SHIFT) | NV34TCL_VTXFMT_TYPE_32_FLOAT);
OUT_RING(chan, (4 << NV30_3D_VTXFMT_SIZE__SHIFT) | NV30_3D_VTXFMT_TYPE_V32_FLOAT);
for(unsigned i = num_outputs; i < elements; ++i)
OUT_RING(chan, NV34TCL_VTXFMT_TYPE_32_FLOAT);
OUT_RING(chan, NV30_3D_VTXFMT_TYPE_V32_FLOAT);
if(nvfx->is_nv4x) {
unsigned i;
@@ -365,7 +365,7 @@ nvfx_vbo_swtnl_validate(struct nvfx_context *nvfx)
}
}
OUT_RING(chan, RING_3D(NV34TCL_VTXBUF_ADDRESS(0), elements));
OUT_RING(chan, RING_3D(NV30_3D_VTXBUF(0), elements));
for (unsigned i = 0; i < elements; i++)
OUT_RING(chan, 0);
@@ -395,11 +395,11 @@ nvfx_vbo_relocate(struct nvfx_context *nvfx)
struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
struct nouveau_bo* bo = nvfx_resource(vb->buffer)->bo;
OUT_RELOC(chan, bo, RING_3D(NV34TCL_VTXBUF_ADDRESS(ve->idx), 1),
OUT_RELOC(chan, bo, RING_3D(NV30_3D_VTXBUF(ve->idx), 1),
vb_flags, 0, 0);
OUT_RELOC(chan, bo, vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride,
vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
0, NV34TCL_VTXBUF_ADDRESS_DMA1);
0, NV30_3D_VTXBUF_DMA1);
}
nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF;
}
@@ -408,7 +408,7 @@ static void
nvfx_idxbuf_emit(struct nvfx_context* nvfx, unsigned ib_flags)
{
struct nouveau_channel* chan = nvfx->screen->base.channel;
unsigned ib_format = (nvfx->idxbuf.index_size == 2) ? NV34TCL_IDXBUF_FORMAT_TYPE_U16 : NV34TCL_IDXBUF_FORMAT_TYPE_U32;
unsigned ib_format = (nvfx->idxbuf.index_size == 2) ? NV30_3D_IDXBUF_FORMAT_TYPE_U16 : NV30_3D_IDXBUF_FORMAT_TYPE_U32;
struct nouveau_bo* bo = nvfx_resource(nvfx->idxbuf.buffer)->bo;
ib_flags |= nvfx->screen->index_buffer_reloc_flags | NOUVEAU_BO_RD;
@@ -416,12 +416,12 @@ nvfx_idxbuf_emit(struct nvfx_context* nvfx, unsigned ib_flags)
MARK_RING(chan, 3, 3);
if(ib_flags & NOUVEAU_BO_DUMMY)
OUT_RELOC(chan, bo, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2), ib_flags, 0, 0);
OUT_RELOC(chan, bo, RING_3D(NV30_3D_IDXBUF_OFFSET, 2), ib_flags, 0, 0);
else
OUT_RING(chan, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2));
OUT_RING(chan, RING_3D(NV30_3D_IDXBUF_OFFSET, 2));
OUT_RELOC(chan, bo, nvfx->idxbuf.offset + 1, ib_flags | NOUVEAU_BO_LOW, 0, 0);
OUT_RELOC(chan, bo, ib_format, ib_flags | NOUVEAU_BO_OR,
0, NV34TCL_IDXBUF_FORMAT_DMA1);
0, NV30_3D_IDXBUF_FORMAT_DMA1);
nvfx->relocs_needed &=~ NVFX_RELOCATE_IDXBUF;
}
@@ -439,27 +439,27 @@ nvfx_idxbuf_relocate(struct nvfx_context* nvfx)
unsigned nvfx_vertex_formats[PIPE_FORMAT_COUNT] =
{
[PIPE_FORMAT_R32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
[PIPE_FORMAT_R32G32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
[PIPE_FORMAT_R32G32B32A32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
[PIPE_FORMAT_R32G32B32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
[PIPE_FORMAT_R16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
[PIPE_FORMAT_R16G16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
[PIPE_FORMAT_R16G16B16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
[PIPE_FORMAT_R16G16B16A16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
[PIPE_FORMAT_R8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
[PIPE_FORMAT_R8G8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
[PIPE_FORMAT_R8G8B8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
[PIPE_FORMAT_R8G8B8A8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
[PIPE_FORMAT_R8G8B8A8_USCALED] = NV34TCL_VTXFMT_TYPE_8_USCALED,
[PIPE_FORMAT_R16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
[PIPE_FORMAT_R16G16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
[PIPE_FORMAT_R16G16B16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
[PIPE_FORMAT_R16G16B16A16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
[PIPE_FORMAT_R16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
[PIPE_FORMAT_R16G16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
[PIPE_FORMAT_R16G16B16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
[PIPE_FORMAT_R16G16B16A16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
[PIPE_FORMAT_R32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
[PIPE_FORMAT_R32G32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
[PIPE_FORMAT_R32G32B32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
[PIPE_FORMAT_R32G32B32A32_FLOAT] = NV30_3D_VTXFMT_TYPE_V32_FLOAT,
[PIPE_FORMAT_R16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
[PIPE_FORMAT_R16G16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
[PIPE_FORMAT_R16G16B16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
[PIPE_FORMAT_R16G16B16A16_FLOAT] = NV30_3D_VTXFMT_TYPE_V16_FLOAT,
[PIPE_FORMAT_R8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
[PIPE_FORMAT_R8G8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
[PIPE_FORMAT_R8G8B8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
[PIPE_FORMAT_R8G8B8A8_UNORM] = NV30_3D_VTXFMT_TYPE_U8_UNORM,
[PIPE_FORMAT_R8G8B8A8_USCALED] = NV30_3D_VTXFMT_TYPE_U8_USCALED,
[PIPE_FORMAT_R16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
[PIPE_FORMAT_R16G16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
[PIPE_FORMAT_R16G16B16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
[PIPE_FORMAT_R16G16B16A16_SNORM] = NV30_3D_VTXFMT_TYPE_V16_SNORM,
[PIPE_FORMAT_R16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
[PIPE_FORMAT_R16G16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
[PIPE_FORMAT_R16G16B16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
[PIPE_FORMAT_R16G16B16A16_SSCALED] = NV30_3D_VTXFMT_TYPE_V16_SSCALED,
};
static void *
@@ -514,7 +514,7 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe,
if(ve->instance_divisor)
{
struct nvfx_low_frequency_element* lfve;
cso->vtxfmt[i] = NV34TCL_VTXFMT_TYPE_32_FLOAT;
cso->vtxfmt[i] = NV30_3D_VTXFMT_TYPE_V32_FLOAT;
//if(ve->frequency == PIPE_ELEMENT_FREQUENCY_CONSTANT)
if(0)
@@ -549,14 +549,14 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe,
if(type)
{
transkey.element[idx].output_format = ve->src_format;
cso->vtxfmt[i] = (ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | type;
cso->vtxfmt[i] = (ncomp << NV30_3D_VTXFMT_SIZE__SHIFT) | type;
}
else
{
unsigned float32[4] = {PIPE_FORMAT_R32_FLOAT, PIPE_FORMAT_R32G32_FLOAT, PIPE_FORMAT_R32G32B32_FLOAT, PIPE_FORMAT_R32G32B32A32_FLOAT};
transkey.element[idx].output_format = float32[ncomp - 1];
cso->needs_translate = TRUE;
cso->vtxfmt[i] = (ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | NV34TCL_VTXFMT_TYPE_32_FLOAT;
cso->vtxfmt[i] = (ncomp << NV30_3D_VTXFMT_SIZE__SHIFT) | NV30_3D_VTXFMT_TYPE_V32_FLOAT;
}
transkey.element[idx].output_offset = transkey.output_stride;
transkey.output_stride += (util_format_get_stride(transkey.element[idx].output_format, 1) + 3) & ~3;
src/gallium/drivers/nvfx/nvfx_vertprog.c
+6 -6
View File
@@ -1310,7 +1310,7 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
* WAIT_RING(chan, 512 * 6);
for (i = 0; i < 512; i++) {
float v[4] = {0.1, 0,2, 0.3, 0.4};
OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_CONST_ID, 5));
OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5));
OUT_RING(chan, i);
OUT_RINGp(chan, (uint32_t *)v, 4);
printf("frob %i\n", i);
@@ -1332,7 +1332,7 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
//printf("upload into %i + %i: %f %f %f %f\n", vp->data->start, i, vpd->value[0], vpd->value[1], vpd->value[2], vpd->value[3]);
OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_CONST_ID, 5));
OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5));
OUT_RING(chan, i + vp->data->start);
OUT_RINGp(chan, (uint32_t *)vpd->value, 4);
}
@@ -1341,10 +1341,10 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
/* Upload vtxprog */
if (upload_code) {
WAIT_RING(chan, 2 + 5 * vp->nr_insns);
OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_FROM_ID, 1));
OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_FROM_ID, 1));
OUT_RING(chan, vp->exec->start);
for (i = 0; i < vp->nr_insns; i++) {
OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_INST(0), 4));
OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_INST(0), 4));
//printf("%08x %08x %08x %08x\n", vp->insns[i].data[0], vp->insns[i].data[1], vp->insns[i].data[2], vp->insns[i].data[3]);
OUT_RINGp(chan, vp->insns[i].data, 4);
}
@@ -1354,10 +1354,10 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
if(nvfx->dirty & (NVFX_NEW_VERTPROG))
{
WAIT_RING(chan, 6);
OUT_RING(chan, RING_3D(NV34TCL_VP_START_FROM_ID, 1));
OUT_RING(chan, RING_3D(NV30_3D_VP_START_FROM_ID, 1));
OUT_RING(chan, vp->exec->start);
if(nvfx->is_nv4x) {
OUT_RING(chan, RING_3D(NV40TCL_VP_ATTRIB_EN, 1));
OUT_RING(chan, RING_3D(NV40_3D_VP_ATTRIB_EN, 1));
OUT_RING(chan, vp->ir);
}
}