nak: Add a trivial register allocator
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
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@@ -3,6 +3,7 @@
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* SPDX-License-Identifier: MIT
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*/
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mod nak_assign_regs;
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mod nak_from_nir;
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mod nak_ir;
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mod nak_opt_copy_prop;
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@@ -46,5 +47,9 @@ pub extern "C" fn nak_compile_shader(
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println!("NAK IR:\n{}", &s);
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s.assign_regs_trivial();
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println!("NAK IR:\n{}", &s);
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std::ptr::null_mut()
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}
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@@ -0,0 +1,82 @@
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/*
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* Copyright © 2022 Collabora, Ltd.
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* SPDX-License-Identifier: MIT
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*/
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#![allow(unstable_name_collisions)]
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use crate::nak_ir::*;
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use crate::util::NextMultipleOf;
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use std::collections::HashMap;
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struct TrivialRegAlloc {
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next_reg: u8,
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next_ureg: u8,
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reg_map: HashMap<SSAValue, Ref>,
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}
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impl TrivialRegAlloc {
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pub fn new() -> TrivialRegAlloc {
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TrivialRegAlloc {
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next_reg: 16, /* Leave some space for FS outputs */
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next_ureg: 0,
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reg_map: HashMap::new(),
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}
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}
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fn alloc_reg(&mut self, file: RegFile, comps: u8) -> Ref {
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let align = comps.next_power_of_two();
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let idx = match file {
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RegFile::GPR => {
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let idx = self.next_reg.next_multiple_of(align);
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self.next_reg = idx + comps;
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idx
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}
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RegFile::UGPR => {
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let idx = self.next_ureg.next_multiple_of(align);
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self.next_ureg = idx + comps;
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idx
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}
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RegFile::Pred | RegFile::UPred => panic!("Not handled"),
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};
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Ref::new_reg(file, idx, comps)
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}
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pub fn rewrite_ref(&mut self, r: &Ref) -> Ref {
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if let Ref::SSA(ssa) = r {
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if let Some(reg) = self.reg_map.get(ssa) {
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*reg
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} else {
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let reg = self.alloc_reg(ssa.file(), ssa.comps());
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self.reg_map.insert(*ssa, reg);
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reg
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}
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} else {
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*r
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}
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}
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pub fn do_alloc(&mut self, s: &mut Shader) {
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for f in &mut s.functions {
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for b in &mut f.blocks {
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for instr in &mut b.instrs {
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for dst in instr.dsts_mut() {
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let new_dst = self.rewrite_ref(&dst);
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*dst = new_dst;
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}
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for src in instr.srcs_mut() {
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let new_src = self.rewrite_ref(&src);
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*src = new_src;
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}
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}
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}
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}
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}
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}
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impl Shader {
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pub fn assign_regs_trivial(&mut self) {
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TrivialRegAlloc::new().do_alloc(self);
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}
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}
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