radeonsi: fix isolines tess factor writes to control ring
Fixes piglit arb_tessellation_shader/execution/isoline{_no_tcs}.shader_test.
Cc: mesa-stable@lists.freedesktop.org
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@@ -2657,10 +2657,18 @@ static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
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lp_build_const_int32(gallivm,
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tess_outer_index * 4), "");
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for (i = 0; i < outer_comps; i++)
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out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
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for (i = 0; i < inner_comps; i++)
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out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
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if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
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/* For isolines, the hardware expects tess factors in the
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* reverse order from what GLSL / TGSI specify.
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*/
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out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
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out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
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} else {
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for (i = 0; i < outer_comps; i++)
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out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
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for (i = 0; i < inner_comps; i++)
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out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
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}
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/* Convert the outputs to vectors for stores. */
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vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
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