i965/vec4: add support for packing vs/gs/tes outputs
Here we create a new output_generic_reg array with the ability to store the dst_reg for each component of user defined varyings. This is needed as the previous code only stored the dst_reg based on the varying location which meant packed varyings would overwrite each other. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
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@@ -114,6 +114,8 @@ public:
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* for the ir->location's used.
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*/
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dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
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dst_reg output_generic_reg[MAX_VARYINGS_INCL_PATCH][4];
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unsigned output_generic_num_components[MAX_VARYINGS_INCL_PATCH][4];
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const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
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int uniforms;
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@@ -269,6 +271,7 @@ public:
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void emit_ndc_computation();
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void emit_psiz_and_flags(dst_reg reg);
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vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying);
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void emit_generic_urb_slot(dst_reg reg, int varying, int component);
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virtual void emit_urb_slot(dst_reg reg, int varying);
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void emit_shader_time_begin();
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@@ -416,7 +416,14 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
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src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F,
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instr->num_components);
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output_reg[varying] = dst_reg(src);
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if (varying >= VARYING_SLOT_VAR0) {
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unsigned c = nir_intrinsic_component(instr);
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unsigned v = varying - VARYING_SLOT_VAR0;
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output_generic_reg[v][c] = dst_reg(src);
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output_generic_num_components[v][c] = instr->num_components;
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} else {
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output_reg[varying] = dst_reg(src);
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}
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break;
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}
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@@ -1272,12 +1272,34 @@ vec4_visitor::emit_generic_urb_slot(dst_reg reg, int varying)
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assert(varying < VARYING_SLOT_MAX);
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assert(output_reg[varying].type == reg.type);
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current_annotation = output_reg_annotation[varying];
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if (output_reg[varying].file != BAD_FILE)
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if (output_reg[varying].file != BAD_FILE) {
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return emit(MOV(reg, src_reg(output_reg[varying])));
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else
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} else
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return NULL;
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}
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void
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vec4_visitor::emit_generic_urb_slot(dst_reg reg, int varying, int component)
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{
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assert(varying < VARYING_SLOT_MAX);
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assert(varying >= VARYING_SLOT_VAR0);
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varying = varying - VARYING_SLOT_VAR0;
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unsigned num_comps = output_generic_num_components[varying][component];
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if (num_comps == 0)
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return;
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assert(output_generic_reg[varying][component].type == reg.type);
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current_annotation = output_reg_annotation[varying];
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if (output_generic_reg[varying][component].file != BAD_FILE) {
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src_reg src = src_reg(output_generic_reg[varying][component]);
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src.swizzle = BRW_SWZ_COMP_OUTPUT(component);
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reg.writemask =
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brw_writemask_for_component_packing(num_comps, component);
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emit(MOV(reg, src));
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}
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}
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void
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vec4_visitor::emit_urb_slot(dst_reg reg, int varying)
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{
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@@ -1317,7 +1339,13 @@ vec4_visitor::emit_urb_slot(dst_reg reg, int varying)
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/* No need to write to this slot */
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break;
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default:
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emit_generic_urb_slot(reg, varying);
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if (varying >= VARYING_SLOT_VAR0) {
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for (int i = 0; i < 4; i++) {
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emit_generic_urb_slot(reg, varying, i);
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}
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} else {
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emit_generic_urb_slot(reg, varying);
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}
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break;
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}
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}
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@@ -1765,6 +1793,9 @@ vec4_visitor::vec4_visitor(const struct brw_compiler *compiler,
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this->current_annotation = NULL;
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memset(this->output_reg_annotation, 0, sizeof(this->output_reg_annotation));
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memset(this->output_generic_num_components, 0,
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sizeof(this->output_generic_num_components));
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this->virtual_grf_start = NULL;
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this->virtual_grf_end = NULL;
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this->live_intervals = NULL;
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