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radeonsi/gfx10: mask DCC tile swizzle by alignment

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DCC alignment can be less than the alignment of the main surface. In that
case, the DCC tile swizzle needs to be masked accordingly. Should have no
impact on pre-gfx10.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Nicolai Hähnle
2018-07-23 09:47:19 +02:00
committed by Marek Olšák
parent 1666ee183e
commit d028440f57
2 changed files with 7 additions and 2 deletions
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src/gallium/drivers/radeonsi/si_descriptors.c
+3 -1
View File
@@ -351,7 +351,9 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
assert(base_level_info->mode == RADEON_SURF_MODE_2D);
}
meta_va |= (uint32_t)tex->surface.tile_swizzle << 8;
unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8;
dcc_tile_swizzle &= tex->surface.dcc_alignment - 1;
meta_va |= dcc_tile_swizzle;
} else if (vi_tc_compat_htile_enabled(tex, first_level)) {
meta_va = tex->buffer.gpu_address + tex->htile_offset;
}
src/gallium/drivers/radeonsi/si_state.c
+4 -1
View File
@@ -3194,7 +3194,10 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
tex->dcc_offset) >> 8;
cb_dcc_base |= tex->surface.tile_swizzle;
unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
cb_dcc_base |= dcc_tile_swizzle;
}
if (sctx->chip_class >= GFX10) {