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r300: Indented both copies of radeon_span.[ch] in preparation for merging.

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This commit is contained in:
Oliver McFadden
2007-05-09 18:01:43 +00:00
parent 2b5ef29a7b
commit cea0c2b144
4 changed files with 159 additions and 187 deletions
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src/mesa/drivers/dri/r300/radeon_span.c
+78 -97
View File
@@ -39,6 +39,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* Keith Whitwell <keith@tungstengraphics.com>
*
*/
#include <unistd.h>
#include "glheader.h"
#include "imports.h"
@@ -51,10 +52,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "drirenderbuffer.h"
#define DBG 0
/*
* Note that all information needed to access pixels in a renderbuffer
* should be obtained through the gl_renderbuffer parameter, not per-context
@@ -85,8 +84,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define HW_UNLOCK()
/* ================================================================
* Color buffer
*/
@@ -101,7 +98,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
#include "spantmp2.h"
/* 32 bit, ARGB8888 color spanline and pixel functions
*/
#define SPANTMP_PIXEL_FMT GL_BGRA
@@ -112,7 +108,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
#include "spantmp2.h"
/* ================================================================
* Depth buffer
*/
@@ -127,59 +122,52 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* too...
*/
static GLuint
radeon_mba_z32( const driRenderbuffer *drb, GLint x, GLint y )
static GLuint radeon_mba_z32(const driRenderbuffer * drb, GLint x, GLint y)
{
GLuint pitch = drb->pitch;
if (1 /*|| drb->depthHasSurface */) {
return 4 * (x + y * pitch);
}
else {
GLuint ba, address = 0; /* a[0..1] = 0 */
GLuint pitch = drb->pitch;
if (1 /*|| drb->depthHasSurface */ ) {
return 4 * (x + y * pitch);
} else {
GLuint ba, address = 0; /* a[0..1] = 0 */
ba = (y / 8) * (pitch / 8) + (x / 8);
ba = (y / 8) * (pitch / 8) + (x / 8);
address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
address |=
(((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
address |= (y & 0x8) << 7; /* a[10] = y[3] */
address |=
(((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
address |= (y & 0x8) << 7; /* a[10] = y[3] */
address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
return address;
}
return address;
}
}
static INLINE GLuint
radeon_mba_z16( const driRenderbuffer *drb, GLint x, GLint y )
radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y)
{
GLuint pitch = drb->pitch;
if (1 /*|| drb->depthHasSurface */) {
return 2 * (x + y * pitch);
}
else {
GLuint ba, address = 0; /* a[0] = 0 */
GLuint pitch = drb->pitch;
if (1 /*|| drb->depthHasSurface */ ) {
return 2 * (x + y * pitch);
} else {
GLuint ba, address = 0; /* a[0] = 0 */
ba = (y / 16) * (pitch / 32) + (x / 32);
ba = (y / 16) * (pitch / 32) + (x / 32);
address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
address |= (x & 0x8) << 4; /* a[7] = x[3] */
address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
address |= (y & 0x8) << 7; /* a[10] = y[3] */
address |= ((x & 0x10) ^ (y & 0x10)) << 7;/* a[11] = x[4] ^ y[4] */
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
address |= (x & 0x8) << 4; /* a[7] = x[3] */
address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
address |= (y & 0x8) << 7; /* a[10] = y[3] */
address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
return address;
}
return address;
}
}
/* 16-bit depth buffer functions
*/
#define WRITE_DEPTH( _x, _y, d ) \
@@ -191,7 +179,6 @@ radeon_mba_z16( const driRenderbuffer *drb, GLint x, GLint y )
#define TAG(x) radeon##x##_z16
#include "depthtmp.h"
/* 24 bit depth, 8 bit stencil depthbuffer functions
*
* Careful: It looks like the R300 uses ZZZS byte order while the R200
@@ -215,7 +202,6 @@ do { \
#define TAG(x) radeon##x##_z24_s8
#include "depthtmp.h"
/* ================================================================
* Stencil buffer
*/
@@ -241,84 +227,79 @@ do { \
#define TAG(x) radeon##x##_z24_s8
#include "stenciltmp.h"
/* Move locking out to get reasonable span performance (10x better
* than doing this in HW_LOCK above). WaitForIdle() is the main
* culprit.
*/
static void radeonSpanRenderStart( GLcontext *ctx )
static void radeonSpanRenderStart(GLcontext * ctx)
{
radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
static int first = 1;
r300ContextPtr r300 = (r300ContextPtr)rmesa;
r300ContextPtr r300 = (r300ContextPtr) rmesa;
if (first) {
r300->span_dlocking = getenv("R300_SPAN_DISABLE_LOCKING") ? 1 : 0;
r300->span_dlocking =
getenv("R300_SPAN_DISABLE_LOCKING") ? 1 : 0;
if (r300->span_dlocking == 0) {
fprintf(stderr, "Try R300_SPAN_DISABLE_LOCKING env var if this hangs.\n");
fprintf(stderr,
"Try R300_SPAN_DISABLE_LOCKING env var if this hangs.\n");
fflush(stderr);
sleep(1);
}
first = 0;
}
if (r300->span_dlocking) {
r300Flush(ctx);
LOCK_HARDWARE( rmesa );
radeonWaitForIdleLocked( rmesa );
UNLOCK_HARDWARE( rmesa );
LOCK_HARDWARE(rmesa);
radeonWaitForIdleLocked(rmesa);
UNLOCK_HARDWARE(rmesa);
return;
}
}
// R300_FIREVERTICES( rmesa );
// old code has flush
r300Flush(ctx);
LOCK_HARDWARE( rmesa );
radeonWaitForIdleLocked( rmesa );
// R300_FIREVERTICES( rmesa );
// old code has flush
r300Flush(ctx);
LOCK_HARDWARE(rmesa);
radeonWaitForIdleLocked(rmesa);
}
static void radeonSpanRenderFinish( GLcontext *ctx )
static void radeonSpanRenderFinish(GLcontext * ctx)
{
radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
r300ContextPtr r300 = (r300ContextPtr)rmesa;
_swrast_flush( ctx );
if (r300->span_dlocking == 0)
UNLOCK_HARDWARE( rmesa );
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
r300ContextPtr r300 = (r300ContextPtr) rmesa;
_swrast_flush(ctx);
if (r300->span_dlocking == 0)
UNLOCK_HARDWARE(rmesa);
}
void radeonInitSpanFuncs( GLcontext *ctx )
void radeonInitSpanFuncs(GLcontext * ctx)
{
struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
swdd->SpanRenderStart = radeonSpanRenderStart;
swdd->SpanRenderFinish = radeonSpanRenderFinish;
struct swrast_device_driver *swdd =
_swrast_GetDeviceDriverReference(ctx);
swdd->SpanRenderStart = radeonSpanRenderStart;
swdd->SpanRenderFinish = radeonSpanRenderFinish;
}
/**
* Plug in the Get/Put routines for the given driRenderbuffer.
*/
void
radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis)
{
if (drb->Base.InternalFormat == GL_RGBA) {
if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {
radeonInitPointers_RGB565(&drb->Base);
}
else {
radeonInitPointers_ARGB8888(&drb->Base);
}
}
else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
radeonInitDepthPointers_z16(&drb->Base);
}
else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
radeonInitDepthPointers_z24_s8(&drb->Base);
}
else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
radeonInitStencilPointers_z24_s8(&drb->Base);
}
if (drb->Base.InternalFormat == GL_RGBA) {
if (vis->redBits == 5 && vis->greenBits == 6
&& vis->blueBits == 5) {
radeonInitPointers_RGB565(&drb->Base);
} else {
radeonInitPointers_ARGB8888(&drb->Base);
}
} else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
radeonInitDepthPointers_z16(&drb->Base);
} else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
radeonInitDepthPointers_z24_s8(&drb->Base);
} else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
radeonInitStencilPointers_z24_s8(&drb->Base);
}
}
src/mesa/drivers/dri/r300/radeon_span.h
+8 -4
View File
@@ -1,10 +1,15 @@
/*
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
VA Linux Systems Inc., Fremont, California.
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
@@ -29,18 +34,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/*
* Authors:
* Gareth Hughes <gareth@valinux.com>
* Keith Whitwell <keith@tungstengraphics.com>
* Kevin E. Martin <martin@valinux.com>
*/
#ifndef __RADEON_SPAN_H__
#define __RADEON_SPAN_H__
#ifdef GLX_DIRECT_RENDERING
#include "drirenderbuffer.h"
extern void radeonInitSpanFuncs(GLcontext * ctx);
extern void radeonSetSpanFunctions(driRenderbuffer *rb, const GLvisual *vis);
#endif
#endif
src/mesa/drivers/dri/radeon/radeon_span.c
+66 -83
View File
@@ -1,9 +1,13 @@
/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.c,v 1.6 2002/10/30 12:51:56 alanh Exp $ */
/**************************************************************************
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
VA Linux Systems Inc., Fremont, California.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining
@@ -47,10 +51,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "drirenderbuffer.h"
#define DBG 0
/*
* Note that all information needed to access pixels in a renderbuffer
* should be obtained through the gl_renderbuffer parameter, not per-context
@@ -81,8 +83,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define HW_UNLOCK()
/* ================================================================
* Color buffer
*/
@@ -97,7 +97,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
#include "spantmp2.h"
/* 32 bit, ARGB8888 color spanline and pixel functions
*/
#define SPANTMP_PIXEL_FMT GL_BGRA
@@ -108,7 +107,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
#include "spantmp2.h"
/* ================================================================
* Depth buffer
*/
@@ -123,59 +121,52 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* too...
*/
static GLuint
radeon_mba_z32( const driRenderbuffer *drb, GLint x, GLint y )
static GLuint radeon_mba_z32(const driRenderbuffer * drb, GLint x, GLint y)
{
GLuint pitch = drb->pitch;
if (drb->depthHasSurface) {
return 4 * (x + y * pitch);
}
else {
GLuint ba, address = 0; /* a[0..1] = 0 */
GLuint pitch = drb->pitch;
if (drb->depthHasSurface) {
return 4 * (x + y * pitch);
} else {
GLuint ba, address = 0; /* a[0..1] = 0 */
ba = (y / 16) * (pitch / 16) + (x / 16);
ba = (y / 16) * (pitch / 16) + (x / 16);
address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
address |=
(((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
address |= (y & 0x8) << 7; /* a[10] = y[3] */
address |=
(((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
address |= (y & 0x8) << 7; /* a[10] = y[3] */
address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
return address;
}
return address;
}
}
static INLINE GLuint
radeon_mba_z16( const driRenderbuffer *drb, GLint x, GLint y )
radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y)
{
GLuint pitch = drb->pitch;
if (drb->depthHasSurface) {
return 2 * (x + y * pitch);
}
else {
GLuint ba, address = 0; /* a[0] = 0 */
GLuint pitch = drb->pitch;
if (drb->depthHasSurface) {
return 2 * (x + y * pitch);
} else {
GLuint ba, address = 0; /* a[0] = 0 */
ba = (y / 16) * (pitch / 32) + (x / 32);
ba = (y / 16) * (pitch / 32) + (x / 32);
address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
address |= (x & 0x8) << 4; /* a[7] = x[3] */
address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
address |= (y & 0x8) << 7; /* a[10] = y[3] */
address |= ((x & 0x10) ^ (y & 0x10)) << 7;/* a[11] = x[4] ^ y[4] */
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
address |= (x & 0x8) << 4; /* a[7] = x[3] */
address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
address |= (y & 0x8) << 7; /* a[10] = y[3] */
address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
return address;
}
return address;
}
}
/* 16-bit depth buffer functions
*/
#define WRITE_DEPTH( _x, _y, d ) \
@@ -187,7 +178,6 @@ radeon_mba_z16( const driRenderbuffer *drb, GLint x, GLint y )
#define TAG(x) radeon##x##_z16
#include "depthtmp.h"
/* 24 bit depth, 8 bit stencil depthbuffer functions
*/
#define WRITE_DEPTH( _x, _y, d ) \
@@ -206,7 +196,6 @@ do { \
#define TAG(x) radeon##x##_z24_s8
#include "depthtmp.h"
/* ================================================================
* Stencil buffer
*/
@@ -233,57 +222,51 @@ do { \
#define TAG(x) radeon##x##_z24_s8
#include "stenciltmp.h"
/* Move locking out to get reasonable span performance (10x better
* than doing this in HW_LOCK above). WaitForIdle() is the main
* culprit.
*/
static void radeonSpanRenderStart( GLcontext *ctx )
static void radeonSpanRenderStart(GLcontext * ctx)
{
radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
RADEON_FIREVERTICES( rmesa );
LOCK_HARDWARE( rmesa );
radeonWaitForIdleLocked( rmesa );
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
RADEON_FIREVERTICES(rmesa);
LOCK_HARDWARE(rmesa);
radeonWaitForIdleLocked(rmesa);
}
static void radeonSpanRenderFinish( GLcontext *ctx )
static void radeonSpanRenderFinish(GLcontext * ctx)
{
radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
_swrast_flush( ctx );
UNLOCK_HARDWARE( rmesa );
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
_swrast_flush(ctx);
UNLOCK_HARDWARE(rmesa);
}
void radeonInitSpanFuncs( GLcontext *ctx )
void radeonInitSpanFuncs(GLcontext * ctx)
{
struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
swdd->SpanRenderStart = radeonSpanRenderStart;
swdd->SpanRenderFinish = radeonSpanRenderFinish;
struct swrast_device_driver *swdd =
_swrast_GetDeviceDriverReference(ctx);
swdd->SpanRenderStart = radeonSpanRenderStart;
swdd->SpanRenderFinish = radeonSpanRenderFinish;
}
/**
* Plug in the Get/Put routines for the given driRenderbuffer.
*/
void
radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis)
{
if (drb->Base.InternalFormat == GL_RGBA) {
if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {
radeonInitPointers_RGB565(&drb->Base);
}
else {
radeonInitPointers_ARGB8888(&drb->Base);
}
}
else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
radeonInitDepthPointers_z16(&drb->Base);
}
else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
radeonInitDepthPointers_z24_s8(&drb->Base);
}
else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
radeonInitStencilPointers_z24_s8(&drb->Base);
}
if (drb->Base.InternalFormat == GL_RGBA) {
if (vis->redBits == 5 && vis->greenBits == 6
&& vis->blueBits == 5) {
radeonInitPointers_RGB565(&drb->Base);
} else {
radeonInitPointers_ARGB8888(&drb->Base);
}
} else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
radeonInitDepthPointers_z16(&drb->Base);
} else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
radeonInitDepthPointers_z24_s8(&drb->Base);
} else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
radeonInitStencilPointers_z24_s8(&drb->Base);
}
}
src/mesa/drivers/dri/radeon/radeon_span.h
+7 -3
View File
@@ -1,8 +1,12 @@
/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.h,v 1.2 2002/02/22 21:45:01 dawes Exp $ */
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
VA Linux Systems Inc., Fremont, California.
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
All Rights Reserved.
@@ -30,8 +34,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/*
* Authors:
* Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
* Keith Whitwell <keith@tungstengraphics.com>
* Kevin E. Martin <martin@valinux.com>
*/
#ifndef __RADEON_SPAN_H__
@@ -40,7 +45,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "drirenderbuffer.h"
extern void radeonInitSpanFuncs( GLcontext *ctx );
extern void radeonSetSpanFunctions(driRenderbuffer *rb, const GLvisual *vis);
#endif