vc4: Disable early Z with computed depth.
We don't tell the hardware whether we're computing depth, so we need to manage early Z state manually. Fixes piglit early-z.
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@@ -142,6 +142,8 @@ struct vc4_compiled_shader {
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/** bitmask of which inputs are color inputs, for flat shade handling. */
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uint32_t color_inputs;
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bool disable_early_z;
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uint8_t num_inputs;
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/* Byte offsets for the start of the vertex attributes 0-7, and the
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@@ -71,7 +71,9 @@ vc4_emit_state(struct pipe_context *pctx)
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vc4->draw_max_y = MAX2(vc4->draw_max_y, maxy);
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}
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if (vc4->dirty & (VC4_DIRTY_RASTERIZER | VC4_DIRTY_ZSA)) {
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if (vc4->dirty & (VC4_DIRTY_RASTERIZER |
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VC4_DIRTY_ZSA |
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VC4_DIRTY_COMPILED_FS)) {
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uint8_t ez_enable_mask_out = ~0;
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/* HW-2905: If the RCL ends up doing a full-res load when
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@@ -83,7 +85,7 @@ vc4_emit_state(struct pipe_context *pctx)
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* was seeing bad rendering on glxgears -samples 4 even in
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* that case.
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*/
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if (vc4->msaa)
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if (vc4->msaa || vc4->prog.fs->disable_early_z)
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ez_enable_mask_out &= ~VC4_CONFIG_BITS_EARLY_Z;
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cl_u8(&bcl, VC4_PACKET_CONFIGURATION_BITS);
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@@ -2253,6 +2253,11 @@ vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
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shader->input_slots[shader->num_inputs] = *slot;
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shader->num_inputs++;
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}
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/* Note: the temporary clone in c->s has been freed. */
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nir_shader *orig_shader = key->shader_state->base.ir.nir;
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if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
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shader->disable_early_z = true;
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} else {
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shader->num_inputs = c->num_inputs;
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