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i965: rename tex_ms to tex_cms

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Prepares for the introduction of non-compressed multi-sampled
lookup used in the blorp programs.

v2: now also taking into account gen8

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
This commit is contained in:
Topi Pohjolainen
2013-12-10 16:36:31 +02:00
parent 3c44e43357
commit ce527a6722
10 changed files with 17 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_defines.h
+1 -1
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@@ -770,7 +770,7 @@ enum opcode {
SHADER_OPCODE_TXL,
SHADER_OPCODE_TXS,
FS_OPCODE_TXB,
SHADER_OPCODE_TXF_MS,
SHADER_OPCODE_TXF_CMS,
SHADER_OPCODE_TXF_MCS,
SHADER_OPCODE_LOD,
SHADER_OPCODE_TG4,
src/mesa/drivers/dri/i965/brw_fs.cpp
+1 -1
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@@ -766,7 +766,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
case FS_OPCODE_TXB:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+2 -2
View File
@@ -425,7 +425,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
case SHADER_OPCODE_TXF:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXF_CMS:
if (brw->gen >= 7)
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
else
@@ -1669,7 +1669,7 @@ fs_generator::generate_code(exec_list *instructions)
case FS_OPCODE_TXB:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+2 -2
View File
@@ -1214,7 +1214,7 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
/* sample index */
emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
mlen += reg_width;
inst = emit(SHADER_OPCODE_TXF_MS, dst);
inst = emit(SHADER_OPCODE_TXF_CMS, dst);
break;
case ir_lod:
inst = emit(SHADER_OPCODE_LOD, dst);
@@ -1408,7 +1408,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst, payload); break;
case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst, payload); break;
case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst, payload); break;
case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_MS, dst, payload); break;
case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_CMS, dst, payload); break;
case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst, payload); break;
case ir_query_levels: inst = emit(SHADER_OPCODE_TXS, dst, payload); break;
case ir_lod: inst = emit(SHADER_OPCODE_LOD, dst, payload); break;
src/mesa/drivers/dri/i965/brw_shader.cpp
+3 -3
View File
@@ -440,8 +440,8 @@ brw_instruction_name(enum opcode op)
return "txs";
case FS_OPCODE_TXB:
return "txb";
case SHADER_OPCODE_TXF_MS:
return "txf_ms";
case SHADER_OPCODE_TXF_CMS:
return "txf_cms";
case SHADER_OPCODE_TXF_MCS:
return "txf_mcs";
case SHADER_OPCODE_TG4:
@@ -538,7 +538,7 @@ backend_instruction::is_tex()
opcode == FS_OPCODE_TXB ||
opcode == SHADER_OPCODE_TXD ||
opcode == SHADER_OPCODE_TXF ||
opcode == SHADER_OPCODE_TXF_MS ||
opcode == SHADER_OPCODE_TXF_CMS ||
opcode == SHADER_OPCODE_TXF_MCS ||
opcode == SHADER_OPCODE_TXL ||
opcode == SHADER_OPCODE_TXS ||
src/mesa/drivers/dri/i965/brw_vec4.cpp
+1 -1
View File
@@ -272,7 +272,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_TG4:
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+2 -2
View File
@@ -299,7 +299,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
case SHADER_OPCODE_TXF:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXF_CMS:
if (brw->gen >= 7)
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
else
@@ -1163,7 +1163,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
case SHADER_OPCODE_TEX:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+1 -1
View File
@@ -2339,7 +2339,7 @@ vec4_visitor::visit(ir_texture *ir)
inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXF);
break;
case ir_txf_ms:
inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXF_MS);
inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXF_CMS);
break;
case ir_txs:
inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXS);
src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
+2 -2
View File
@@ -194,7 +194,7 @@ gen8_fs_generator::generate_tex(fs_inst *ir,
case SHADER_OPCODE_TXF:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXF_CMS:
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
break;
case SHADER_OPCODE_TXF_MCS:
@@ -863,7 +863,7 @@ gen8_fs_generator::generate_code(exec_list *instructions)
case FS_OPCODE_TXB:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
+2 -2
View File
@@ -82,7 +82,7 @@ gen8_vec4_generator::generate_tex(vec4_instruction *ir, struct brw_reg dst)
case SHADER_OPCODE_TXF:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXF_CMS:
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
break;
case SHADER_OPCODE_TXF_MCS:
@@ -694,7 +694,7 @@ gen8_vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
case SHADER_OPCODE_TEX:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS: