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radeonsi: add a cs parameter into si_cp_release_mem

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Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2019-01-22 17:22:18 -05:00
parent 9624855f13
commit ce264d19a0
5 changed files with 9 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeonsi/si_fence.c
+2 -3
View File
@@ -66,13 +66,12 @@ struct si_multi_fence {
* \param old_value Previous fence value (for a bug workaround)
* \param new_value Fence value to write for this event.
*/
void si_cp_release_mem(struct si_context *ctx,
void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
unsigned event, unsigned event_flags,
unsigned dst_sel, unsigned int_sel, unsigned data_sel,
struct si_resource *buf, uint64_t va,
uint32_t new_fence, unsigned query_type)
{
struct radeon_cmdbuf *cs = ctx->gfx_cs;
unsigned op = EVENT_TYPE(event) |
EVENT_INDEX(event == V_028A90_CS_DONE ||
event == V_028A90_PS_DONE ? 6 : 5) |
@@ -269,7 +268,7 @@ static void si_fine_fence_set(struct si_context *ctx,
radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf,
RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
si_cp_release_mem(ctx,
si_cp_release_mem(ctx, ctx->gfx_cs,
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
EOP_DATA_SEL_VALUE_32BIT,
src/gallium/drivers/radeonsi/si_perfcounter.c
+1 -1
View File
@@ -690,7 +690,7 @@ static void si_pc_emit_stop(struct si_context *sctx,
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
EOP_DATA_SEL_VALUE_32BIT,
buffer, va, 0, SI_NOT_QUERY);
src/gallium/drivers/radeonsi/si_pipe.h
+1 -1
View File
@@ -1274,7 +1274,7 @@ void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst
uint64_t offset, uint64_t size, unsigned value);
/* si_fence.c */
void si_cp_release_mem(struct si_context *ctx,
void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
unsigned event, unsigned event_flags,
unsigned dst_sel, unsigned int_sel, unsigned data_sel,
struct si_resource *buf, uint64_t va,
src/gallium/drivers/radeonsi/si_query.c
+3 -3
View File
@@ -820,7 +820,7 @@ static void si_query_hw_do_emit_start(struct si_context *sctx,
emit_sample_streamout(cs, va + 32 * stream, stream);
break;
case PIPE_QUERY_TIME_ELAPSED:
si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
EOP_DATA_SEL_TIMESTAMP, NULL, va,
0, query->b.type);
@@ -896,7 +896,7 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx,
va += 8;
/* fall through */
case PIPE_QUERY_TIMESTAMP:
si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
EOP_DATA_SEL_TIMESTAMP, NULL, va,
0, query->b.type);
@@ -921,7 +921,7 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx,
RADEON_PRIO_QUERY);
if (fence_va) {
si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
EOP_DATA_SEL_VALUE_32BIT,
query->buffer.buf, fence_va, 0x80000000,
src/gallium/drivers/radeonsi/si_state_draw.c
+2 -2
View File
@@ -945,7 +945,7 @@ void si_emit_cache_flush(struct si_context *sctx)
/* Necessary for DCC */
if (sctx->chip_class == GFX8)
si_cp_release_mem(sctx,
si_cp_release_mem(sctx, cs,
V_028A90_FLUSH_AND_INV_CB_DATA_TS,
0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
EOP_DATA_SEL_DISCARD, NULL,
@@ -1062,7 +1062,7 @@ void si_emit_cache_flush(struct si_context *sctx)
va = sctx->wait_mem_scratch->gpu_address;
sctx->wait_mem_number++;
si_cp_release_mem(sctx, cb_db_event, tc_flags,
si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
EOP_DST_SEL_MEM,
EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
EOP_DATA_SEL_VALUE_32BIT,