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intel/fs: Support 64-bit SEL_EXEC on Gen11+

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>
This commit is contained in:
Jason Ekstrand
2020-10-26 13:34:04 -05:00
committed by Marge Bot
parent 58bcb5401d
commit cdedc82329
1 changed files with 19 additions and 5 deletions
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24
src/intel/compiler/brw_fs_generator.cpp
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@@ -2459,11 +2459,25 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
case SHADER_OPCODE_SEL_EXEC:
assert(inst->force_writemask_all);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, dst, src[1]);
brw_set_default_mask_control(p, BRW_MASK_ENABLE);
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, dst, src[0]);
if (type_sz(dst.type) > 4 && !devinfo->has_64bit_float) {
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 0),
subscript(src[1], BRW_REGISTER_TYPE_UD, 0));
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 1),
subscript(src[1], BRW_REGISTER_TYPE_UD, 1));
brw_set_default_mask_control(p, BRW_MASK_ENABLE);
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 0),
subscript(src[0], BRW_REGISTER_TYPE_UD, 0));
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 1),
subscript(src[0], BRW_REGISTER_TYPE_UD, 1));
} else {
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, dst, src[1]);
brw_set_default_mask_control(p, BRW_MASK_ENABLE);
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, dst, src[0]);
}
break;
case SHADER_OPCODE_QUAD_SWIZZLE: