anv/blorp: add missing cs stall on compute pipe control

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37715>

src/intel/blorp/blorp.h

@@ -149,6 +149,9 @@ enum blorp_batch_flags {
     * Mostly for debug
     */
    BLORP_BATCH_DISABLE_VF_DISTRIBUTION = BITFIELD_BIT(6),
+
+   /* Blorp is running on compute engine. */
+   BLORP_BATCH_COMPUTE_ENGINE = BITFIELD_BIT(7),
 };
 
 struct blorp_batch {

src/intel/blorp/blorp_genX_exec_brw.h

@@ -1835,9 +1835,18 @@ blorp_exec_compute(struct blorp_batch *batch, const struct blorp_params *params)
    /*
     * TDOD: Add INTEL_NEEDS_WA_14025112257 check once HSD is propogated for all
     * other impacted platforms.
+    *
+    * BSpec 47112 (xe), 56551 (xe2): Instruction_PIPE_CONTROL (ComputeCS):
+    * SW must follow below programming restrictions when programming
+    * PIPE_CONTROL command:
+    *
+    * "Command Streamer Stall Enable" must be always set.
+    * ...
     */
    if (devinfo->ver >= 20) {
       blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
+         pc.CommandStreamerStallEnable =
+            batch->flags & BLORP_BATCH_COMPUTE_ENGINE;
          pc.StateCacheInvalidationEnable = true;
       }
    }

src/intel/vulkan/anv_blorp.c

@@ -185,6 +185,9 @@ anv_blorp_batch_init(struct anv_cmd_buffer *cmd_buffer,
    if (!cmd_buffer->device->physical->instance->enable_vf_distribution)
       flags |= BLORP_BATCH_DISABLE_VF_DISTRIBUTION;
 
+   if (cmd_buffer->batch.engine_class == INTEL_ENGINE_CLASS_COMPUTE)
+      flags |= BLORP_BATCH_COMPUTE_ENGINE;
+
    blorp_batch_init(&cmd_buffer->device->blorp.context, batch, cmd_buffer, flags);
 }