i965/fs: Remove bogus field prog_data->dispatch_width.

Despite the name, this field wasn't being set to the dispatch width at
all; it was always 8.  The only place it was used was that the
constant buffer read length was aligned to it, and as far as I can
tell from the docs, there is no need to align this value to the
dispatch width; aligning it to a multiple of 8 is sufficient.  So I've
just replaced it with a hardcoded 8.

v2: In gen6_wm_state, use brw->wm.base.push_const_size for consistency
with VS and GS state upload.

Reviewed-by: Eric Anholt <eric@anholt.net>

src/mesa/drivers/dri/i965/brw_context.h

@@ -380,7 +380,6 @@ struct brw_wm_prog_data {
    GLuint nr_params;       /**< number of float params/constants */
    GLuint nr_pull_params;
    bool dual_src_blend;
-   int dispatch_width;
    uint32_t prog_offset_16;
 
    /**

src/mesa/drivers/dri/i965/brw_fs.cpp

@@ -3188,8 +3188,6 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
       }
    }
 
-   c->prog_data.dispatch_width = 8;
-
    fs_generator g(brw, c, prog, fp, v.dual_src_output.file != BAD_FILE);
    const unsigned *generated = g.generate_assembly(&v.instructions,
                                                    simd16_instructions,

src/mesa/drivers/dri/i965/gen6_wm_state.c

@@ -78,8 +78,7 @@ gen6_upload_wm_push_constants(struct brw_context *brw)
 	 printf("\n");
       }
 
-      brw->wm.base.push_const_size =
-         ALIGN(prog_data->nr_params, prog_data->dispatch_width) / 8;
+      brw->wm.base.push_const_size = ALIGN(prog_data->nr_params, 8) / 8;
    }
 }
 
@@ -123,8 +122,7 @@ upload_wm_state(struct brw_context *brw)
        * state flags from gen6_upload_wm_push_constants.
        */
       OUT_BATCH(brw->wm.base.push_const_offset +
-		ALIGN(brw->wm.prog_data->nr_params,
-		      brw->wm.prog_data->dispatch_width) / 8 - 1);
+		brw->wm.base.push_const_size - 1);
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);