pan/midgard: Simplify spillability test
Let's not worry about spilling twice in a bundle; that's too restrictive. We'll need to change the schedule itself -- unfortunately, this can have second-order effects due to pipeline registers. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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@@ -704,36 +704,18 @@ mir_choose_spill_node(
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for (unsigned i = 0; i < ctx->temp_count; ++i)
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lcra_set_node_spill_cost(l, i, cost[i]);
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/* We can't spill any bundles that contain unspills. This could be
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* optimized to allow use of r27 to spill twice per bundle, but if
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* you're at the point of optimizing spilling, it's too late.
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*
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* We also can't double-spill. */
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/* We can't spill a previously spilled value or an unspill */
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mir_foreach_block(ctx, block) {
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mir_foreach_bundle_in_block(block, bun) {
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bool no_spill = false;
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mir_foreach_instr_global(ctx, ins) {
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if (ins->no_spill) {
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if (ins->dest < ctx->temp_count)
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lcra_set_node_spill_cost(l, ins->dest, -1);
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for (unsigned i = 0; i < bun->instruction_count; ++i) {
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no_spill |= bun->instructions[i]->no_spill;
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mir_foreach_src(ins, s) {
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unsigned src = ins->src[s];
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if (bun->instructions[i]->no_spill) {
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mir_foreach_src(bun->instructions[i], s) {
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unsigned src = bun->instructions[i]->src[s];
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if (src < ctx->temp_count)
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lcra_set_node_spill_cost(l, src, -1);
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}
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}
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}
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if (!no_spill)
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continue;
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for (unsigned i = 0; i < bun->instruction_count; ++i) {
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unsigned dest = bun->instructions[i]->dest;
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if (dest < ctx->temp_count)
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lcra_set_node_spill_cost(l, dest, -1);
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if (src < ctx->temp_count)
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lcra_set_node_spill_cost(l, src, -1);
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}
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}
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}
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