intel/isl: Don't over-allocate CLEAR_COLOR size to use whole cache line

At the time this was added to fix some test failures. But it seems that
the failures were happening due to missing cache flushes, so
this extra space is no longer neccessary.

Fixes: 37b4eacc ("intel/isl: Resize clear color buffer to full cacheline")
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24768>

src/intel/isl/isl.c

@@ -307,8 +307,7 @@ isl_device_init(struct isl_device *dev,
    dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
    dev->ss.align = isl_align(dev->ss.size, 32);
 
-   dev->ss.clear_color_state_size =
-      isl_align(CLEAR_COLOR_length(info) * 4, 64);
+   dev->ss.clear_color_state_size = CLEAR_COLOR_length(info) * 4;
    dev->ss.clear_color_state_offset =
       RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4;