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radv/winsys: handle encoder queue padding/submits.

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The encoder queue doesn't like padding at all, don't pad in the sysmem
paths for encoder queue.

The encoder queue will be using on gfx11 for decoding.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>
This commit is contained in:
Dave Airlie
2023-03-17 14:13:06 +10:00
committed by Marge Bot
parent 2fdf75dadf
commit ca7a2e508d
1 changed files with 6 additions and 2 deletions
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8
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
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@@ -299,6 +299,8 @@ static uint32_t get_nop_packet(struct radv_amdgpu_cs *cs)
return PKT2_NOP_PAD;
case AMDGPU_HW_IP_VCN_DEC:
return 0x81FF;
case AMDGPU_HW_IP_VCN_ENC:
return 0; /* NOPs are illegal in encode, so don't pad */
default:
unreachable("Unknown IP type");
}
@@ -413,8 +415,10 @@ radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
*cs->ib_size_ptr |= cs->base.cdw;
} else {
/* Pad the CS with NOP packets. */
while (!cs->base.cdw || (cs->base.cdw & ib_pad_dw_mask))
radeon_emit(&cs->base, nop_packet);
if (ip_type != AMDGPU_HW_IP_VCN_ENC) {
while (!cs->base.cdw || (cs->base.cdw & ib_pad_dw_mask))
radeon_emit(&cs->base, nop_packet);
}
/* Append the current (last) IB to the array of old IB buffers. */
radv_amdgpu_cs_add_old_ib_buffer(cs);