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radeonsi: don't emit partial flushes at the end of IBs (v2)

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The kernel sort of does the same thing with fences.

v2: do emit partial flushes on SI

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2017-06-16 14:25:34 +02:00
parent 5352174d49
commit c9040dc9e7
1 changed files with 9 additions and 5 deletions
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src/gallium/drivers/radeonsi/si_hw_context.c
+9 -5
View File
@@ -129,13 +129,17 @@ void si_context_gfx_flush(void *context, unsigned flags,
r600_preflush_suspend_features(&ctx->b);
ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
SI_CONTEXT_PS_PARTIAL_FLUSH;
/* DRM 3.1.0 doesn't flush TC for VI correctly. */
if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) {
ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH |
SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_INV_VMEM_L1;
} else if (ctx->b.chip_class == SI) {
/* The kernel doesn't wait for idle before doing SURFACE_SYNC. */
ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH;
}
si_emit_cache_flush(ctx);