i965: Fix up the VUE handling for SNB, and hopefully clarify comments.
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@@ -180,10 +180,12 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
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c->first_output = reg;
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c->first_overflow_output = 0;
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if (intel->is_ironlake)
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mrf = 8;
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if (intel->gen >= 6)
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mrf = 6;
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else if (intel->is_ironlake)
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mrf = 8;
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else
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mrf = 4;
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mrf = 4;
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for (i = 0; i < VERT_RESULT_MAX; i++) {
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if (c->prog_data.outputs_written & BITFIELD64_BIT(i)) {
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@@ -1195,7 +1197,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
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struct brw_reg pos = c->regs[PROGRAM_OUTPUT][VERT_RESULT_HPOS];
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struct brw_reg ndc;
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int eot;
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GLuint len_vertext_header = 2;
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GLuint len_vertex_header = 2;
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if (c->key.copy_edgeflag) {
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brw_MOV(p,
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@@ -1203,12 +1205,14 @@ static void emit_vertex_write( struct brw_vs_compile *c)
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get_reg(c, PROGRAM_INPUT, VERT_ATTRIB_EDGEFLAG));
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}
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/* Build ndc coords */
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ndc = get_tmp(c);
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/* ndc = 1.0 / pos.w */
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emit_math1(c, BRW_MATH_FUNCTION_INV, ndc, brw_swizzle1(pos, 3), BRW_MATH_PRECISION_FULL);
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/* ndc.xyz = pos * ndc */
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brw_MUL(p, brw_writemask(ndc, WRITEMASK_XYZ), pos, ndc);
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if (intel->gen < 6) {
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/* Build ndc coords */
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ndc = get_tmp(c);
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/* ndc = 1.0 / pos.w */
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emit_math1(c, BRW_MATH_FUNCTION_INV, ndc, brw_swizzle1(pos, 3), BRW_MATH_PRECISION_FULL);
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/* ndc.xyz = pos * ndc */
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brw_MUL(p, brw_writemask(ndc, WRITEMASK_XYZ), pos, ndc);
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}
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/* Update the header for point size, user clipping flags, and -ve rhw
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* workaround.
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@@ -1271,21 +1275,41 @@ static void emit_vertex_write( struct brw_vs_compile *c)
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* of zeros followed by two sets of NDC coordinates:
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*/
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brw_set_access_mode(p, BRW_ALIGN_1);
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brw_MOV(p, offset(m0, 2), ndc);
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if (intel->is_ironlake || intel->gen >= 6) {
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/* There are 20 DWs (D0-D19) in VUE vertex header on Ironlake */
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brw_MOV(p, offset(m0, 3), pos); /* a portion of vertex header */
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/* m4, m5 contain the distances from vertex to the user clip planeXXX.
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* Seems it is useless for us.
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* m6 is used for aligning, so that the remainder of vertex element is
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* reg-aligned.
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*/
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brw_MOV(p, offset(m0, 7), pos); /* the remainder of vertex element */
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len_vertext_header = 6;
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if (intel->gen >= 6) {
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/* There are 16 DWs (D0-D15) in VUE header on Sandybridge:
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* dword 0-3 (m1) of the header is indices, point width, clip flags.
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* dword 4-7 (m2) is the 4D space position
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* dword 8-15 (m3,m4) of the vertex header is the user clip distance.
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* m5 is the first vertex data we fill, which is the vertex position.
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*/
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brw_MOV(p, offset(m0, 2), pos);
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brw_MOV(p, offset(m0, 5), pos);
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len_vertex_header = 4;
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} else if (intel->is_ironlake) {
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/* There are 20 DWs (D0-D19) in VUE header on Ironlake:
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* dword 0-3 (m1) of the header is indices, point width, clip flags.
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* dword 4-7 (m2) is the ndc position (set above)
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* dword 8-11 (m3) of the vertex header is the 4D space position
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* dword 12-19 (m4,m5) of the vertex header is the user clip distance.
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* m6 is a pad so that the vertex element data is aligned
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* m7 is the first vertex data we fill, which is the vertex position.
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*/
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brw_MOV(p, offset(m0, 2), ndc);
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brw_MOV(p, offset(m0, 3), pos);
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brw_MOV(p, offset(m0, 7), pos);
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len_vertex_header = 6;
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} else {
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brw_MOV(p, offset(m0, 3), pos);
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len_vertext_header = 2;
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/* There are 8 dwords in VUE header pre-Ironlake:
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* dword 0-3 (m1) is indices, point width, clip flags.
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* dword 4-7 (m2) is ndc position (set above)
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*
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* dword 8-11 (m3) is the first vertex data, which we always have be the
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* vertex position.
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*/
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brw_MOV(p, offset(m0, 2), ndc);
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brw_MOV(p, offset(m0, 3), pos);
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len_vertex_header = 2;
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}
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eot = (c->first_overflow_output == 0);
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@@ -1296,7 +1320,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
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c->r0, /* src */
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0, /* allocate */
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1, /* used */
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MIN2(c->nr_outputs + 1 + len_vertext_header, (BRW_MAX_MRF-1)), /* msg len */
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MIN2(c->nr_outputs + 1 + len_vertex_header, (BRW_MAX_MRF-1)), /* msg len */
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0, /* response len */
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eot, /* eot */
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eot, /* writes complete */
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