ac/nir/ngg: fix emitting streamout output by using packed location

In RadeonSI, they are packed but not in RADV, so don't rely on driver
locations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19343>
This commit is contained in:
Samuel Pitoiset
2022-10-27 16:07:43 +02:00
committed by Marge Bot
parent 1c37a8342c
commit c84dbd189b
3 changed files with 10 additions and 17 deletions
+1 -1
View File
@@ -2445,7 +2445,7 @@ update_layered_rendering_state(struct zink_context *ctx)
VKCTX(CmdPushConstants)(
ctx->batch.state->cmdbuf,
zink_screen(ctx->base.screen)->gfx_push_constant_layout,
VK_SHADER_STAGE_VERTEX_BIT | VK_SHADER_STAGE_GEOMETRY_BIT | VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
VK_SHADER_STAGE_ALL_GRAPHICS,
offsetof(struct zink_gfx_push_constant, framebuffer_is_layered), sizeof(unsigned),
&framebffer_is_layered);
}
+3 -3
View File
@@ -181,7 +181,7 @@ zink_bind_vertex_state(struct zink_batch *batch, struct zink_context *ctx,
ALWAYS_INLINE static void
update_drawid(struct zink_context *ctx, unsigned draw_id)
{
VKCTX(CmdPushConstants)(ctx->batch.state->cmdbuf, ctx->curr_program->base.layout, VK_SHADER_STAGE_VERTEX_BIT,
VKCTX(CmdPushConstants)(ctx->batch.state->cmdbuf, ctx->curr_program->base.layout, VK_SHADER_STAGE_ALL_GRAPHICS,
offsetof(struct zink_gfx_push_constant, draw_id), sizeof(unsigned),
&draw_id);
}
@@ -766,12 +766,12 @@ zink_draw(struct pipe_context *pctx,
if (reads_basevertex) {
unsigned draw_mode_is_indexed = index_size > 0;
VKCTX(CmdPushConstants)(batch->state->cmdbuf, ctx->curr_program->base.layout, VK_SHADER_STAGE_VERTEX_BIT,
VKCTX(CmdPushConstants)(batch->state->cmdbuf, ctx->curr_program->base.layout, VK_SHADER_STAGE_ALL_GRAPHICS,
offsetof(struct zink_gfx_push_constant, draw_mode_is_indexed), sizeof(unsigned),
&draw_mode_is_indexed);
}
if (ctx->curr_program->shaders[MESA_SHADER_TESS_CTRL] && ctx->curr_program->shaders[MESA_SHADER_TESS_CTRL]->is_generated) {
VKCTX(CmdPushConstants)(batch->state->cmdbuf, ctx->curr_program->base.layout, VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT,
VKCTX(CmdPushConstants)(batch->state->cmdbuf, ctx->curr_program->base.layout, VK_SHADER_STAGE_ALL_GRAPHICS,
offsetof(struct zink_gfx_push_constant, default_inner_level), sizeof(float) * 6,
&ctx->tess_levels[0]);
}
+6 -13
View File
@@ -792,21 +792,14 @@ zink_pipeline_layout_create(struct zink_screen *screen, VkDescriptorSetLayout *d
plci.pSetLayouts = dsl;
plci.setLayoutCount = num_dsl;
VkPushConstantRange pcr[3] = {0};
VkPushConstantRange pcr;
if (!is_compute) {
pcr[0].stageFlags = VK_SHADER_STAGE_VERTEX_BIT;
pcr[0].offset = offsetof(struct zink_gfx_push_constant, draw_mode_is_indexed);
pcr[0].size = 2 * sizeof(unsigned);
pcr[1].stageFlags =
VK_SHADER_STAGE_VERTEX_BIT | VK_SHADER_STAGE_GEOMETRY_BIT | VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
pcr[1].offset = offsetof(struct zink_gfx_push_constant, framebuffer_is_layered);
pcr[1].size = 1 * sizeof(unsigned);
pcr[2].stageFlags = VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
pcr[2].offset = offsetof(struct zink_gfx_push_constant, default_inner_level);
pcr[2].size = sizeof(float) * 6;
plci.pushConstantRangeCount = ARRAY_SIZE(pcr);
pcr.stageFlags = VK_SHADER_STAGE_ALL_GRAPHICS;
pcr.offset = 0;
pcr.size = sizeof(struct zink_gfx_push_constant);
plci.pushConstantRangeCount = 1;
plci.pPushConstantRanges = &pcr;
}
plci.pPushConstantRanges = pcr;
VkPipelineLayout layout;
VkResult result = VKSCR(CreatePipelineLayout)(screen->dev, &plci, NULL, &layout);