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iris: Insert buffer-local memory barriers for indirect draw parameters.

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This adds buffer-local barriers so any required synchronization
commands are emitted before a buffer object is used as source for
indirect draw parameters.  An unconditional PIPE_CONTROL meant to
flush the contents of the draw count buffer can now be removed, since
it's redundant with the more accurate buffer-local barrier introduced
here, which should avoid flushing in cases where the buffer wasn't
written by any incoherent cache since the last flush.

(Rebased by Kenneth Graunke.)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12691>
This commit is contained in:
Francisco Jerez
2020-05-11 14:43:41 -07:00
committed by Marge Bot
parent 51f022cc03
commit c677e76483
2 changed files with 13 additions and 8 deletions
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src/gallium/drivers/iris/iris_draw.c
+13 -4
View File
@@ -187,10 +187,19 @@ iris_indirect_draw_vbo(struct iris_context *ice,
struct pipe_draw_info info = *dinfo;
struct pipe_draw_indirect_info indirect = *dindirect;
if (indirect.indirect_draw_count &&
ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) {
/* Upload MI_PREDICATE_RESULT to GPR15.*/
batch->screen->vtbl.load_register_reg64(batch, CS_GPR(15), MI_PREDICATE_RESULT);
iris_emit_buffer_barrier_for(batch, iris_resource_bo(indirect.buffer),
IRIS_DOMAIN_VF_READ);
if (indirect.indirect_draw_count) {
struct iris_bo *draw_count_bo =
iris_resource_bo(indirect.indirect_draw_count);
iris_emit_buffer_barrier_for(batch, draw_count_bo,
IRIS_DOMAIN_OTHER_READ);
if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) {
/* Upload MI_PREDICATE_RESULT to GPR15.*/
batch->screen->vtbl.load_register_reg64(batch, CS_GPR(15), MI_PREDICATE_RESULT);
}
}
const uint64_t orig_dirty = ice->state.dirty;
src/gallium/drivers/iris/iris_state.c
-4
View File
@@ -6735,10 +6735,6 @@ iris_upload_render_state(struct iris_context *ice,
unsigned draw_count_offset =
indirect->indirect_draw_count_offset;
iris_emit_pipe_control_flush(batch,
"ensure indirect draw buffer is flushed",
PIPE_CONTROL_FLUSH_ENABLE);
if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) {
struct mi_builder b;
mi_builder_init(&b, &batch->screen->devinfo, batch);