radeonsi: remove some definitions and helpers from r600_pipe_common.h

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

src/gallium/drivers/radeon/r600_pipe_common.h

@@ -46,8 +46,6 @@
 
 struct u_log_context;
 
-#define ATI_VENDOR_ID 0x1002
-
 #define R600_RESOURCE_FLAG_TRANSFER		(PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH	(PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
 #define R600_RESOURCE_FLAG_FORCE_TILING		(PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
@@ -61,11 +59,6 @@ struct u_log_context;
 #define R600_CONTEXT_FLUSH_FOR_RENDER_COND	(1u << 3)
 #define R600_CONTEXT_PRIVATE_FLAG		(1u << 4)
 
-/* special primitive types */
-#define R600_PRIM_RECTANGLE_LIST	PIPE_PRIM_MAX
-
-#define R600_NOT_QUERY		0xffffffff
-
 /* Debug flags. */
 enum {
 	/* Shader logging options: */
@@ -136,18 +129,6 @@ enum {
 
 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
 
-enum r600_coherency {
-	R600_COHERENCY_NONE, /* no cache flushes needed */
-	R600_COHERENCY_SHADER,
-	R600_COHERENCY_CB_META,
-};
-
-#ifdef PIPE_ARCH_BIG_ENDIAN
-#define R600_BIG_ENDIAN 1
-#else
-#define R600_BIG_ENDIAN 0
-#endif
-
 struct r600_common_context;
 struct r600_perfcounters;
 struct tgsi_shader_info;
@@ -787,96 +768,13 @@ r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 	pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 }
 
-static inline void
-r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
-{
-	struct r600_common_context *rctx = (struct r600_common_context *)ctx;
-	struct r600_resource *res = (struct r600_resource *)r;
-
-	if (res) {
-		/* Add memory usage for need_gfx_cs_space */
-		rctx->vram += res->vram_usage;
-		rctx->gtt += res->gart_usage;
-	}
-}
-
-#define     SQ_TEX_XY_FILTER_POINT                         0x00
-#define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
-#define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
-#define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
-
-static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
-{
-	if (filter == PIPE_TEX_FILTER_LINEAR)
-		return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
-				     : SQ_TEX_XY_FILTER_BILINEAR;
-	else
-		return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
-				     : SQ_TEX_XY_FILTER_POINT;
-}
-
-static inline unsigned r600_tex_aniso_filter(unsigned filter)
-{
-	if (filter < 2)
-		return 0;
-	if (filter < 4)
-		return 1;
-	if (filter < 8)
-		return 2;
-	if (filter < 16)
-		return 3;
-	return 4;
-}
-
-static inline enum radeon_bo_priority
-r600_get_sampler_view_priority(struct r600_resource *res)
-{
-	if (res->b.b.target == PIPE_BUFFER)
-		return RADEON_PRIO_SAMPLER_BUFFER;
-
-	if (res->b.b.nr_samples > 1)
-		return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
-
-	return RADEON_PRIO_SAMPLER_TEXTURE;
-}
-
-static inline bool
-r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
-{
-	return (stencil_sampler && tex->can_sample_s) ||
-	       (!stencil_sampler && tex->can_sample_z);
-}
-
 static inline bool
 vi_dcc_enabled(struct r600_texture *tex, unsigned level)
 {
 	return tex->dcc_offset && level < tex->surface.num_dcc_levels;
 }
 
-static inline bool
-r600_htile_enabled(struct r600_texture *tex, unsigned level)
-{
-	return tex->htile_offset && level == 0;
-}
-
-static inline bool
-vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
-{
-	assert(!tex->tc_compatible_htile || tex->htile_offset);
-	return tex->tc_compatible_htile && level == 0;
-}
-
-#define COMPUTE_DBG(rscreen, fmt, args...) \
-	do { \
-		if ((rscreen->b.debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
-	} while (0);
-
 #define R600_ERR(fmt, args...) \
 	fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 
-static inline int S_FIXED(float value, unsigned frac_bits)
-{
-	return value * (1 << frac_bits);
-}
-
 #endif

src/gallium/drivers/radeonsi/si_blit.c

@@ -315,7 +315,7 @@ si_decompress_depth(struct si_context *sctx,
 		levels_z = level_mask & tex->dirty_level_mask;
 
 		if (levels_z) {
-			if (r600_can_sample_zs(tex, false))
+			if (si_can_sample_zs(tex, false))
 				inplace_planes |= PIPE_MASK_Z;
 			else
 				copy_planes |= PIPE_MASK_Z;
@@ -325,7 +325,7 @@ si_decompress_depth(struct si_context *sctx,
 		levels_s = level_mask & tex->stencil_dirty_level_mask;
 
 		if (levels_s) {
-			if (r600_can_sample_zs(tex, true))
+			if (si_can_sample_zs(tex, true))
 				inplace_planes |= PIPE_MASK_S;
 			else
 				copy_planes |= PIPE_MASK_S;
@@ -374,7 +374,7 @@ si_decompress_depth(struct si_context *sctx,
 	}
 
 	if (inplace_planes) {
-		bool has_htile = r600_htile_enabled(tex, first_level);
+		bool has_htile = si_htile_enabled(tex, first_level);
 		bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
 
 		/* Don't decompress if there is no HTILE or when HTILE is

src/gallium/drivers/radeonsi/si_clear.c

@@ -551,7 +551,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
 	}
 
 	if (zstex &&
-	    r600_htile_enabled(zstex, zsbuf->u.tex.level) &&
+	    si_htile_enabled(zstex, zsbuf->u.tex.level) &&
 	    zsbuf->u.tex.first_layer == 0 &&
 	    zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
 		/* TC-compatible HTILE only supports depth clears to 0 or 1. */

src/gallium/drivers/radeonsi/si_compute.c

@@ -33,6 +33,11 @@
 #include "si_compute.h"
 #include "sid.h"
 
+#define COMPUTE_DBG(rscreen, fmt, args...) \
+	do { \
+		if ((rscreen->b.debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
+	} while (0);
+
 struct dispatch_packet {
 	uint16_t header;
 	uint16_t setup;
@@ -813,11 +818,11 @@ static void si_launch_grid(
 	si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
 
 	/* Add buffer sizes for memory checking in need_cs_space. */
-	r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
+	si_context_add_resource_size(ctx, &program->shader.bo->b.b);
 	/* TODO: add the scratch buffer */
 
 	if (info->indirect) {
-		r600_context_add_resource_size(ctx, info->indirect);
+		si_context_add_resource_size(ctx, info->indirect);
 
 		/* Indirect buffers use TC L2 on GFX9, but not older hw. */
 		if (sctx->b.chip_class <= VI &&

src/gallium/drivers/radeonsi/si_cp_dma.c

@@ -165,9 +165,9 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
 
 	if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
 		/* Count memory usage in so that need_cs_space can take it into account. */
-		r600_context_add_resource_size(&sctx->b.b, dst);
+		si_context_add_resource_size(&sctx->b.b, dst);
 		if (src)
-			r600_context_add_resource_size(&sctx->b.b, src);
+			si_context_add_resource_size(&sctx->b.b, src);
 	}
 
 	if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))

src/gallium/drivers/radeonsi/si_descriptors.c

@@ -199,6 +199,18 @@ si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc
 
 /* SAMPLER VIEWS */
 
+static inline enum radeon_bo_priority
+si_get_sampler_view_priority(struct r600_resource *res)
+{
+	if (res->b.b.target == PIPE_BUFFER)
+		return RADEON_PRIO_SAMPLER_BUFFER;
+
+	if (res->b.b.nr_samples > 1)
+		return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
+
+	return RADEON_PRIO_SAMPLER_TEXTURE;
+}
+
 static unsigned
 si_sampler_and_image_descriptors_idx(unsigned shader)
 {
@@ -237,12 +249,12 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
 	if (resource->target != PIPE_BUFFER) {
 		struct r600_texture *tex = (struct r600_texture*)resource;
 
-		if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil_sampler))
+		if (tex->is_depth && !si_can_sample_zs(tex, is_stencil_sampler))
 			resource = &tex->flushed_depth_texture->resource.b.b;
 	}
 
 	rres = (struct r600_resource*)resource;
-	priority = r600_get_sampler_view_priority(rres);
+	priority = si_get_sampler_view_priority(rres);
 
 	radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
 					    rres, usage, priority,
@@ -306,7 +318,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 {
 	uint64_t va, meta_va = 0;
 
-	if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
+	if (tex->is_depth && !si_can_sample_zs(tex, is_stencil)) {
 		tex = tex->flushed_depth_texture;
 		is_stencil = false;
 	}

src/gallium/drivers/radeonsi/si_hw_context.c

@@ -265,8 +265,8 @@ void si_begin_new_cs(struct si_context *ctx)
 
 	si_mark_atom_dirty(ctx, &ctx->scratch_state);
 	if (ctx->scratch_buffer) {
-		r600_context_add_resource_size(&ctx->b.b,
-					       &ctx->scratch_buffer->b.b);
+		si_context_add_resource_size(&ctx->b.b,
+					     &ctx->scratch_buffer->b.b);
 	}
 
 	if (ctx->streamout.suspended) {

src/gallium/drivers/radeonsi/si_perfcounter.c

@@ -612,7 +612,7 @@ static void si_pc_emit_stop(struct r600_common_context *ctx,
 
 	si_gfx_write_event_eop(ctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
 				 EOP_DATA_SEL_VALUE_32BIT,
-				 buffer, va, 0, R600_NOT_QUERY);
+				 buffer, va, 0, SI_NOT_QUERY);
 	si_gfx_wait_fence(ctx, va, 0, 0xffffffff);
 
 	radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));

src/gallium/drivers/radeonsi/si_pipe.h

@@ -34,6 +34,10 @@
 #define SI_BIG_ENDIAN 0
 #endif
 
+#define ATI_VENDOR_ID 0x1002
+
+#define SI_NOT_QUERY		0xffffffff
+
 /* The base vertex and primitive restart can be any number, but we must pick
  * one which will mean "unknown" for the purpose of state tracking and
  * the number shouldn't be a commonly-used one. */
@@ -596,6 +600,12 @@ void si_init_clear_functions(struct si_context *sctx);
 			   SI_CPDMA_SKIP_GFX_SYNC | \
 			   SI_CPDMA_SKIP_BO_LIST_UPDATE)
 
+enum r600_coherency {
+	R600_COHERENCY_NONE, /* no cache flushes needed */
+	R600_COHERENCY_SHADER,
+	R600_COHERENCY_CB_META,
+};
+
 void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 		     uint64_t offset, uint64_t size, unsigned value,
 		     enum r600_coherency coher);
@@ -659,6 +669,19 @@ void si_init_viewport_functions(struct si_context *ctx);
  * common helpers
  */
 
+static inline void
+si_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
+{
+	struct r600_common_context *rctx = (struct r600_common_context *)ctx;
+	struct r600_resource *res = (struct r600_resource *)r;
+
+	if (res) {
+		/* Add memory usage for need_gfx_cs_space */
+		rctx->vram += res->vram_usage;
+		rctx->gtt += res->gart_usage;
+	}
+}
+
 static inline void
 si_invalidate_draw_sh_constants(struct si_context *sctx)
 {
@@ -793,4 +816,24 @@ si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 	}
 }
 
+static inline bool
+si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
+{
+	return (stencil_sampler && tex->can_sample_s) ||
+	       (!stencil_sampler && tex->can_sample_z);
+}
+
+static inline bool
+si_htile_enabled(struct r600_texture *tex, unsigned level)
+{
+	return tex->htile_offset && level == 0;
+}
+
+static inline bool
+vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
+{
+	assert(!tex->tc_compatible_htile || tex->htile_offset);
+	return tex->tc_compatible_htile && level == 0;
+}
+
 #endif

src/gallium/drivers/radeonsi/si_state.c

@@ -2531,7 +2531,7 @@ static void si_init_depth_surface(struct si_context *sctx,
 		surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
 				      S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
 
-		if (r600_htile_enabled(rtex, level)) {
+		if (si_htile_enabled(rtex, level)) {
 			z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
 				  S_028038_ALLOW_EXPCLEAR(1);
 
@@ -2609,7 +2609,7 @@ static void si_init_depth_surface(struct si_context *sctx,
 		surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
 								levelinfo->nblk_y) / 64 - 1);
 
-		if (r600_htile_enabled(rtex, level)) {
+		if (si_htile_enabled(rtex, level)) {
 			z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
 				  S_028040_ALLOW_EXPCLEAR(1);
 
@@ -2861,7 +2861,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
 		if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
 			sctx->framebuffer.CB_has_shader_readable_metadata = true;
 
-		r600_context_add_resource_size(ctx, surf->base.texture);
+		si_context_add_resource_size(ctx, surf->base.texture);
 
 		p_atomic_inc(&rtex->framebuffers_bound);
 
@@ -2885,7 +2885,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
 		if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
 			sctx->framebuffer.DB_has_shader_readable_metadata = true;
 
-		r600_context_add_resource_size(ctx, surf->base.texture);
+		si_context_add_resource_size(ctx, surf->base.texture);
 	}
 
 	si_update_poly_offset_state(sctx);
@@ -3893,7 +3893,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
 	pipe_format = state->format;
 
 	/* Depth/stencil texturing sometimes needs separate texture. */
-	if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
+	if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
 		if (!tmp->flushed_depth_texture &&
 		    !si_init_flushed_depth_texture(ctx, texture, NULL)) {
 			pipe_resource_reference(&view->base.texture, NULL);
@@ -4053,6 +4053,34 @@ do { \
 	       S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
 }
 
+static inline int S_FIXED(float value, unsigned frac_bits)
+{
+	return value * (1 << frac_bits);
+}
+
+static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
+{
+	if (filter == PIPE_TEX_FILTER_LINEAR)
+		return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
+				     : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
+	else
+		return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
+				     : V_008F38_SQ_TEX_XY_FILTER_POINT;
+}
+
+static inline unsigned si_tex_aniso_filter(unsigned filter)
+{
+	if (filter < 2)
+		return 0;
+	if (filter < 4)
+		return 1;
+	if (filter < 8)
+		return 2;
+	if (filter < 16)
+		return 3;
+	return 4;
+}
+
 static void *si_create_sampler_state(struct pipe_context *ctx,
 				     const struct pipe_sampler_state *state)
 {
@@ -4061,7 +4089,7 @@ static void *si_create_sampler_state(struct pipe_context *ctx,
 	struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
 	unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
 						       : state->max_anisotropy;
-	unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
+	unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
 	union pipe_color_union clamped_border_color;
 
 	if (!rstate) {
@@ -4085,8 +4113,8 @@ static void *si_create_sampler_state(struct pipe_context *ctx,
 			  S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
 			  S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
 	rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
-			  S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
-			  S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
+			  S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
+			  S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
 			  S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
 			  S_008F38_MIP_POINT_PRECLAMP(0) |
 			  S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
@@ -4365,7 +4393,7 @@ static void si_set_vertex_buffers(struct pipe_context *ctx,
 			pipe_resource_reference(&dsti->buffer.resource, buf);
 			dsti->buffer_offset = src->buffer_offset;
 			dsti->stride = src->stride;
-			r600_context_add_resource_size(ctx, buf);
+			si_context_add_resource_size(ctx, buf);
 			if (buf)
 				r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
 		}

src/gallium/drivers/radeonsi/si_state_draw.c

@@ -33,6 +33,9 @@
 
 #include "ac_debug.h"
 
+/* special primitive types */
+#define SI_PRIM_RECTANGLE_LIST	PIPE_PRIM_MAX
+
 static unsigned si_conv_pipe_prim(unsigned mode)
 {
         static const unsigned prim_conv[] = {
@@ -51,7 +54,7 @@ static unsigned si_conv_pipe_prim(unsigned mode)
 		[PIPE_PRIM_TRIANGLES_ADJACENCY]		= V_008958_DI_PT_TRILIST_ADJ,
 		[PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]	= V_008958_DI_PT_TRISTRIP_ADJ,
 		[PIPE_PRIM_PATCHES]			= V_008958_DI_PT_PATCH,
-		[R600_PRIM_RECTANGLE_LIST]		= V_008958_DI_PT_RECTLIST
+		[SI_PRIM_RECTANGLE_LIST]		= V_008958_DI_PT_RECTLIST
         };
 	assert(mode < ARRAY_SIZE(prim_conv));
 	return prim_conv[mode];
@@ -75,7 +78,7 @@ static unsigned si_conv_prim_to_gs_out(unsigned mode)
 		[PIPE_PRIM_TRIANGLES_ADJACENCY]		= V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 		[PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]	= V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 		[PIPE_PRIM_PATCHES]			= V_028A6C_OUTPRIM_TYPE_POINTLIST,
-		[R600_PRIM_RECTANGLE_LIST]		= V_028A6C_OUTPRIM_TYPE_TRISTRIP
+		[SI_PRIM_RECTANGLE_LIST]		= V_028A6C_OUTPRIM_TYPE_TRISTRIP
 	};
 	assert(mode < ARRAY_SIZE(prim_conv));
 
@@ -311,7 +314,7 @@ static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
 	switch (info->mode) {
 	case PIPE_PRIM_PATCHES:
 		return info->count / info->vertices_per_patch;
-	case R600_PRIM_RECTANGLE_LIST:
+	case SI_PRIM_RECTANGLE_LIST:
 		return info->count / 3;
 	default:
 		return u_prims_for_vertices(info->mode, info->count);
@@ -446,7 +449,7 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
 
 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
 {
-	for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
+	for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
 	for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
 	for (int multi_instances = 0; multi_instances < 2; multi_instances++)
 	for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
@@ -907,7 +910,7 @@ void si_emit_cache_flush(struct si_context *sctx)
 			if (rctx->chip_class == VI)
 				si_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
 							 0, EOP_DATA_SEL_DISCARD, NULL,
-							 0, 0, R600_NOT_QUERY);
+							 0, 0, SI_NOT_QUERY);
 		}
 		if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
 			cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
@@ -1023,7 +1026,7 @@ void si_emit_cache_flush(struct si_context *sctx)
 		si_gfx_write_event_eop(rctx, cb_db_event, tc_flags,
 					 EOP_DATA_SEL_VALUE_32BIT,
 					 sctx->wait_mem_scratch, va,
-					 sctx->wait_mem_number, R600_NOT_QUERY);
+					 sctx->wait_mem_number, SI_NOT_QUERY);
 		si_gfx_wait_fence(rctx, va, sctx->wait_mem_number, 0xffffffff);
 	}
 
@@ -1379,7 +1382,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 		struct pipe_draw_indirect_info *indirect = info->indirect;
 
 		/* Add the buffer size for memory checking in need_cs_space. */
-		r600_context_add_resource_size(ctx, indirect->buffer);
+		si_context_add_resource_size(ctx, indirect->buffer);
 
 		/* Indirect buffers use TC L2 on GFX9, but not older hw. */
 		if (sctx->b.chip_class <= VI) {
@@ -1536,7 +1539,7 @@ void si_draw_rectangle(struct blitter_context *blitter,
 	pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
 
 	struct pipe_draw_info info = {};
-	info.mode = R600_PRIM_RECTANGLE_LIST;
+	info.mode = SI_PRIM_RECTANGLE_LIST;
 	info.count = 3;
 	info.instance_count = num_instances;
 

src/gallium/drivers/radeonsi/si_state_shaders.c

@@ -3029,8 +3029,8 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
 				return false;
 
 			si_mark_atom_dirty(sctx, &sctx->scratch_state);
-			r600_context_add_resource_size(&sctx->b.b,
-						       &sctx->scratch_buffer->b.b);
+			si_context_add_resource_size(&sctx->b.b,
+						     &sctx->scratch_buffer->b.b);
 		}
 
 		if (!si_update_scratch_relocs(sctx))

src/gallium/drivers/radeonsi/si_state_streamout.c

@@ -152,7 +152,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
 		if (!targets[i])
 			continue;
 
-		r600_context_add_resource_size(ctx, targets[i]->buffer);
+		si_context_add_resource_size(ctx, targets[i]->buffer);
 		enabled_mask |= 1 << i;
 
 		if (offsets[i] == ((unsigned)-1))