i965: Remove some dead code optimization passes.
The old brw_remove_grf_to_mrf_moves() pass is obsolete and replaced by fs_visitor::compute_to_mrf(). The old brw_remove_duplicate_mrf_moves() pass is obsolete and replaced by fs_visitor::remove_duplicate_mrf_writes(). The remaining pass, brw_set_dp4_dependency_control(), is currently unused, but could be, so I'm leaving it for now. Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke
@@ -86,550 +86,6 @@ const struct brw_instruction_info brw_opcodes[128] = {
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[BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 },
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};
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static INLINE
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bool brw_is_arithmetic_inst(const struct brw_instruction *inst)
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{
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return brw_opcodes[inst->header.opcode].is_arith;
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}
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static const GLuint inst_stride[7] = {
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[0] = 0,
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[1] = 1,
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[2] = 2,
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[3] = 4,
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[4] = 8,
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[5] = 16,
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[6] = 32
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};
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static const GLuint inst_type_size[8] = {
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[BRW_REGISTER_TYPE_UD] = 4,
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[BRW_REGISTER_TYPE_D] = 4,
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[BRW_REGISTER_TYPE_UW] = 2,
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[BRW_REGISTER_TYPE_W] = 2,
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[BRW_REGISTER_TYPE_UB] = 1,
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[BRW_REGISTER_TYPE_B] = 1,
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[BRW_REGISTER_TYPE_F] = 4
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};
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static INLINE bool
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brw_is_grf_written(const struct brw_instruction *inst,
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int reg_index, int size,
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int gen)
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{
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if (brw_opcodes[inst->header.opcode].ndst == 0)
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return false;
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if (inst->bits1.da1.dest_address_mode != BRW_ADDRESS_DIRECT)
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if (inst->bits1.ia1.dest_reg_file == BRW_GENERAL_REGISTER_FILE)
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return true;
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if (inst->bits1.da1.dest_reg_file != BRW_GENERAL_REGISTER_FILE)
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return false;
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const int reg_start = reg_index * REG_SIZE;
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const int reg_end = reg_start + size;
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const int type_size = inst_type_size[inst->bits1.da1.dest_reg_type];
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const int write_start = inst->bits1.da1.dest_reg_nr*REG_SIZE
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+ inst->bits1.da1.dest_subreg_nr;
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int length, write_end;
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/* SEND is specific */
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if (inst->header.opcode == BRW_OPCODE_SEND) {
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if (gen >= 5)
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length = inst->bits3.generic_gen5.response_length*REG_SIZE;
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else
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length = inst->bits3.generic.response_length*REG_SIZE;
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}
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else {
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length = 1 << inst->header.execution_size;
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length *= type_size;
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length *= inst->bits1.da1.dest_horiz_stride;
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}
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/* If the two intervals intersect, we overwrite the register */
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write_end = write_start + length;
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const int left = MAX2(write_start, reg_start);
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const int right = MIN2(write_end, reg_end);
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return left < right;
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}
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static bool
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brw_is_mrf_written_alu(const struct brw_instruction *inst,
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int reg_index, int size)
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{
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if (brw_opcodes[inst->header.opcode].ndst == 0)
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return false;
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if (inst->bits1.da1.dest_reg_file != BRW_MESSAGE_REGISTER_FILE)
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return false;
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if (inst->bits1.da1.dest_address_mode != BRW_ADDRESS_DIRECT)
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return true;
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const int reg_start = reg_index * REG_SIZE;
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const int reg_end = reg_start + size;
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const int mrf_index = inst->bits1.da1.dest_reg_nr & 0x0f;
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const int is_compr4 = inst->bits1.da1.dest_reg_nr & BRW_MRF_COMPR4;
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const int type_size = inst_type_size[inst->bits1.da1.dest_reg_type];
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/* We use compr4 with a size != 16 elements. Strange, we conservatively
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* consider that we are writing the register.
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*/
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if (is_compr4 && inst->header.execution_size != BRW_EXECUTE_16)
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return true;
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/* Here we write mrf_{i} and mrf_{i+4}. So we read two times 8 elements */
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if (is_compr4) {
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const int length = 8 * type_size * inst->bits1.da1.dest_horiz_stride;
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/* First 8-way register */
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const int write_start0 = mrf_index*REG_SIZE
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+ inst->bits1.da1.dest_subreg_nr;
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const int write_end0 = write_start0 + length;
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/* Second 8-way register */
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const int write_start1 = (mrf_index+4)*REG_SIZE
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+ inst->bits1.da1.dest_subreg_nr;
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const int write_end1 = write_start1 + length;
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/* If the two intervals intersect, we overwrite the register */
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const int left0 = MAX2(write_start0, reg_start);
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const int right0 = MIN2(write_end0, reg_end);
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const int left1 = MAX2(write_start1, reg_start);
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const int right1 = MIN2(write_end1, reg_end);
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if (left0 < right0 || left1 < right1)
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return true;
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}
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else {
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int length;
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length = 1 << inst->header.execution_size;
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length *= type_size;
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length *= inst->bits1.da1.dest_horiz_stride;
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/* If the two intervals intersect, we write into the register */
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const int write_start = inst->bits1.da1.dest_reg_nr*REG_SIZE
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+ inst->bits1.da1.dest_subreg_nr;
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const int write_end = write_start + length;
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const int left = MAX2(write_start, reg_start);
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const int right = MIN2(write_end, reg_end);
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if (left < right)
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return true;
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}
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return false;
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}
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/* SEND may perform an implicit mov to a mrf register */
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static bool
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brw_is_mrf_written_send(const struct brw_instruction *inst,
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int reg_index, int size)
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{
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const int reg_start = reg_index * REG_SIZE;
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const int reg_end = reg_start + size;
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const int mrf_start = inst->header.destreg__conditionalmod;
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const int write_start = mrf_start * REG_SIZE;
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const int write_end = write_start + REG_SIZE;
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const int left = MAX2(write_start, reg_start);
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const int right = MIN2(write_end, reg_end);
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if (inst->header.opcode != BRW_OPCODE_SEND ||
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inst->bits1.da1.src0_reg_file == 0)
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return false;
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return left < right;
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}
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/* Specific path for message register since we need to handle the compr4 case */
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static INLINE bool
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brw_is_mrf_written(const struct brw_instruction *inst, int reg_index, int size)
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{
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return (brw_is_mrf_written_alu(inst, reg_index, size) ||
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brw_is_mrf_written_send(inst, reg_index, size));
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}
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static INLINE bool
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brw_is_mrf_read(const struct brw_instruction *inst,
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int reg_index, int size, int gen)
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{
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if (inst->header.opcode != BRW_OPCODE_SEND)
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return false;
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if (inst->bits2.da1.src0_address_mode != BRW_ADDRESS_DIRECT)
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return true;
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const int reg_start = reg_index*REG_SIZE;
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const int reg_end = reg_start + size;
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int length, read_start, read_end;
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if (gen >= 5)
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length = inst->bits3.generic_gen5.msg_length*REG_SIZE;
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else
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length = inst->bits3.generic.msg_length*REG_SIZE;
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/* Look if SEND uses an implicit mov. In that case, we read one less register
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* (but we write it)
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*/
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if (inst->bits1.da1.src0_reg_file != 0)
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read_start = inst->header.destreg__conditionalmod;
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else {
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length--;
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read_start = inst->header.destreg__conditionalmod + 1;
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}
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read_start *= REG_SIZE;
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read_end = read_start + length;
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const int left = MAX2(read_start, reg_start);
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const int right = MIN2(read_end, reg_end);
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return left < right;
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}
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static INLINE bool
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brw_is_grf_read(const struct brw_instruction *inst, int reg_index, int size)
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{
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int i, j;
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if (brw_opcodes[inst->header.opcode].nsrc == 0)
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return false;
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/* Look at first source. We must take into account register regions to
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* monitor carefully the read. Note that we are a bit too conservative here
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* since we do not take into account the fact that some complete registers
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* may be skipped
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*/
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if (brw_opcodes[inst->header.opcode].nsrc >= 1) {
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if (inst->bits2.da1.src0_address_mode != BRW_ADDRESS_DIRECT)
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if (inst->bits1.ia1.src0_reg_file == BRW_GENERAL_REGISTER_FILE)
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return true;
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if (inst->bits1.da1.src0_reg_file != BRW_GENERAL_REGISTER_FILE)
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return false;
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const int reg_start = reg_index*REG_SIZE;
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const int reg_end = reg_start + size;
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/* See if at least one of this element intersects the interval */
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const int type_size = inst_type_size[inst->bits1.da1.src0_reg_type];
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const int elem_num = 1 << inst->header.execution_size;
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const int width = 1 << inst->bits2.da1.src0_width;
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const int row_num = elem_num >> inst->bits2.da1.src0_width;
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const int hs = type_size*inst_stride[inst->bits2.da1.src0_horiz_stride];
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const int vs = type_size*inst_stride[inst->bits2.da1.src0_vert_stride];
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int row_start = inst->bits2.da1.src0_reg_nr*REG_SIZE
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+ inst->bits2.da1.src0_subreg_nr;
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for (j = 0; j < row_num; ++j) {
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int write_start = row_start;
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for (i = 0; i < width; ++i) {
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const int write_end = write_start + type_size;
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const int left = write_start > reg_start ? write_start : reg_start;
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const int right = write_end < reg_end ? write_end : reg_end;
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if (left < right)
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return true;
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write_start += hs;
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}
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row_start += vs;
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}
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}
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/* Second src register */
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if (brw_opcodes[inst->header.opcode].nsrc >= 2) {
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if (inst->bits3.da1.src1_address_mode != BRW_ADDRESS_DIRECT)
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if (inst->bits1.ia1.src1_reg_file == BRW_GENERAL_REGISTER_FILE)
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return true;
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if (inst->bits1.da1.src1_reg_file != BRW_GENERAL_REGISTER_FILE)
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return false;
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const int reg_start = reg_index*REG_SIZE;
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const int reg_end = reg_start + size;
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/* See if at least one of this element intersects the interval */
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const int type_size = inst_type_size[inst->bits1.da1.src1_reg_type];
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const int elem_num = 1 << inst->header.execution_size;
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const int width = 1 << inst->bits3.da1.src1_width;
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const int row_num = elem_num >> inst->bits3.da1.src1_width;
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const int hs = type_size*inst_stride[inst->bits3.da1.src1_horiz_stride];
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const int vs = type_size*inst_stride[inst->bits3.da1.src1_vert_stride];
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int row_start = inst->bits3.da1.src1_reg_nr*REG_SIZE
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+ inst->bits3.da1.src1_subreg_nr;
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for (j = 0; j < row_num; ++j) {
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int write_start = row_start;
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for (i = 0; i < width; ++i) {
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const int write_end = write_start + type_size;
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const int left = write_start > reg_start ? write_start : reg_start;
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const int right = write_end < reg_end ? write_end : reg_end;
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if (left < right)
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return true;
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write_start += hs;
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}
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row_start += vs;
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}
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}
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return false;
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}
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static INLINE bool
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brw_is_control_done(const struct brw_instruction *mov) {
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return
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mov->header.dependency_control != 0 ||
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mov->header.thread_control != 0 ||
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mov->header.mask_control != 0 ||
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mov->header.saturate != 0 ||
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mov->header.debug_control != 0;
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}
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static INLINE bool
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brw_is_predicated(const struct brw_instruction *mov) {
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return mov->header.predicate_control != 0;
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}
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static INLINE bool
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brw_is_grf_to_mrf_mov(const struct brw_instruction *mov,
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int *mrf_index,
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int *grf_index,
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bool *is_compr4)
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{
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if (brw_is_predicated(mov) ||
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brw_is_control_done(mov) ||
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mov->header.debug_control != 0)
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return false;
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if (mov->bits1.da1.dest_address_mode != BRW_ADDRESS_DIRECT ||
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mov->bits1.da1.dest_reg_file != BRW_MESSAGE_REGISTER_FILE ||
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mov->bits1.da1.dest_reg_type != BRW_REGISTER_TYPE_F ||
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mov->bits1.da1.dest_horiz_stride != BRW_HORIZONTAL_STRIDE_1 ||
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mov->bits1.da1.dest_subreg_nr != 0)
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return false;
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if (mov->bits2.da1.src0_address_mode != BRW_ADDRESS_DIRECT ||
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mov->bits1.da1.src0_reg_file != BRW_GENERAL_REGISTER_FILE ||
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mov->bits1.da1.src0_reg_type != BRW_REGISTER_TYPE_F ||
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mov->bits2.da1.src0_width != BRW_WIDTH_8 ||
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mov->bits2.da1.src0_horiz_stride != BRW_HORIZONTAL_STRIDE_1 ||
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mov->bits2.da1.src0_vert_stride != BRW_VERTICAL_STRIDE_8 ||
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mov->bits2.da1.src0_subreg_nr != 0 ||
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mov->bits2.da1.src0_abs != 0 ||
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mov->bits2.da1.src0_negate != 0)
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return false;
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*grf_index = mov->bits2.da1.src0_reg_nr;
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*mrf_index = mov->bits1.da1.dest_reg_nr & 0x0f;
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*is_compr4 = (mov->bits1.da1.dest_reg_nr & BRW_MRF_COMPR4) != 0;
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return true;
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}
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static INLINE bool
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brw_is_grf_straight_write(const struct brw_instruction *inst, int grf_index)
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{
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/* remark: no problem to predicate a SEL instruction */
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if ((!brw_is_predicated(inst) || inst->header.opcode == BRW_OPCODE_SEL) &&
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brw_is_control_done(inst) == false &&
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inst->header.execution_size == 4 &&
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inst->header.access_mode == BRW_ALIGN_1 &&
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inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT &&
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inst->bits1.da1.dest_reg_file == BRW_GENERAL_REGISTER_FILE &&
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inst->bits1.da1.dest_reg_type == BRW_REGISTER_TYPE_F &&
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inst->bits1.da1.dest_horiz_stride == BRW_HORIZONTAL_STRIDE_1 &&
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inst->bits1.da1.dest_reg_nr == grf_index &&
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inst->bits1.da1.dest_subreg_nr == 0 &&
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brw_is_arithmetic_inst(inst))
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return true;
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return false;
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}
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static INLINE bool
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brw_inst_are_equal(const struct brw_instruction *src0,
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const struct brw_instruction *src1)
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{
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const GLuint *field0 = (GLuint *) src0;
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const GLuint *field1 = (GLuint *) src1;
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return field0[0] == field1[0] &&
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field0[1] == field1[1] &&
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field0[2] == field1[2] &&
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field0[3] == field1[3];
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}
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static INLINE void
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brw_inst_copy(struct brw_instruction *dst,
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const struct brw_instruction *src)
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{
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GLuint *field_dst = (GLuint *) dst;
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const GLuint *field_src = (GLuint *) src;
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field_dst[0] = field_src[0];
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field_dst[1] = field_src[1];
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field_dst[2] = field_src[2];
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field_dst[3] = field_src[3];
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}
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static void brw_remove_inst(struct brw_compile *p, const bool *removeInst)
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{
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int i, nr_insn = 0, to = 0, from = 0;
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for (from = 0; from < p->nr_insn; ++from) {
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if (removeInst[from])
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continue;
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if(to != from)
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brw_inst_copy(p->store + to, p->store + from);
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to++;
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}
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for (i = 0; i < p->nr_insn; ++i)
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if (removeInst[i] == false)
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nr_insn++;
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p->nr_insn = nr_insn;
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}
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/* The gen code emitter generates a lot of duplications in the
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* grf-to-mrf moves, for example when texture sampling with the same
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* coordinates from multiple textures.. Here, we monitor same mov
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* grf-to-mrf instrutions and remove repeated ones where the operands
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* and dst ahven't changed in between.
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*/
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void brw_remove_duplicate_mrf_moves(struct brw_compile *p)
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{
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const int gen = p->brw->intel.gen;
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int i, j;
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bool *removeInst = calloc(sizeof(bool), p->nr_insn);
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for (i = 0; i < p->nr_insn; i++) {
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if (removeInst[i])
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continue;
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const struct brw_instruction *mov = p->store + i;
|
||||
int mrf_index, grf_index;
|
||||
bool is_compr4;
|
||||
|
||||
/* Only consider _straight_ grf-to-mrf moves */
|
||||
if (!brw_is_grf_to_mrf_mov(mov, &mrf_index, &grf_index, &is_compr4))
|
||||
continue;
|
||||
|
||||
const int mrf_index0 = mrf_index;
|
||||
const int mrf_index1 = is_compr4 ? mrf_index0+4 : mrf_index0+1;
|
||||
const int simd16_size = 2 * REG_SIZE;
|
||||
|
||||
for (j = i + 1; j < p->nr_insn; j++) {
|
||||
const struct brw_instruction *inst = p->store + j;
|
||||
|
||||
if (brw_inst_are_equal(mov, inst)) {
|
||||
removeInst[j] = true;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (brw_is_grf_written(inst, grf_index, simd16_size, gen) ||
|
||||
brw_is_mrf_written(inst, mrf_index0, REG_SIZE) ||
|
||||
brw_is_mrf_written(inst, mrf_index1, REG_SIZE))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
brw_remove_inst(p, removeInst);
|
||||
free(removeInst);
|
||||
}
|
||||
|
||||
/* Replace moves to MRFs where the value moved is the result of a
|
||||
* normal arithmetic operation with computation right into the MRF.
|
||||
*/
|
||||
void brw_remove_grf_to_mrf_moves(struct brw_compile *p)
|
||||
{
|
||||
int i, j, prev;
|
||||
struct brw_context *brw = p->brw;
|
||||
const int gen = brw->intel.gen;
|
||||
const int simd16_size = 2*REG_SIZE;
|
||||
|
||||
bool *removeInst = calloc(sizeof(bool), p->nr_insn);
|
||||
assert(removeInst);
|
||||
|
||||
for (i = 0; i < p->nr_insn; i++) {
|
||||
if (removeInst[i])
|
||||
continue;
|
||||
|
||||
struct brw_instruction *grf_inst = NULL;
|
||||
const struct brw_instruction *mov = p->store + i;
|
||||
int mrf_index, grf_index;
|
||||
bool is_compr4;
|
||||
|
||||
/* Only consider _straight_ grf-to-mrf moves */
|
||||
if (!brw_is_grf_to_mrf_mov(mov, &mrf_index, &grf_index, &is_compr4))
|
||||
continue;
|
||||
|
||||
/* Using comp4 enables a stride of 4 for this instruction */
|
||||
const int mrf_index0 = mrf_index;
|
||||
const int mrf_index1 = is_compr4 ? mrf_index+4 : mrf_index+1;
|
||||
|
||||
/* Look where the register has been set */
|
||||
prev = i;
|
||||
bool potential_remove = false;
|
||||
while (prev--) {
|
||||
|
||||
/* If _one_ instruction writes the grf, we try to remove the mov */
|
||||
struct brw_instruction *inst = p->store + prev;
|
||||
if (brw_is_grf_straight_write(inst, grf_index)) {
|
||||
potential_remove = true;
|
||||
grf_inst = inst;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (potential_remove == false)
|
||||
continue;
|
||||
removeInst[i] = true;
|
||||
|
||||
/* Monitor first the section of code between the grf computation and the
|
||||
* mov. Here we cannot read or write both mrf and grf register
|
||||
*/
|
||||
for (j = prev + 1; j < i; ++j) {
|
||||
struct brw_instruction *inst = p->store + j;
|
||||
if (removeInst[j])
|
||||
continue;
|
||||
if (brw_is_grf_written(inst, grf_index, simd16_size, gen) ||
|
||||
brw_is_grf_read(inst, grf_index, simd16_size) ||
|
||||
brw_is_mrf_written(inst, mrf_index0, REG_SIZE) ||
|
||||
brw_is_mrf_written(inst, mrf_index1, REG_SIZE) ||
|
||||
brw_is_mrf_read(inst, mrf_index0, REG_SIZE, gen) ||
|
||||
brw_is_mrf_read(inst, mrf_index1, REG_SIZE, gen)) {
|
||||
removeInst[i] = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* After the mov, we can read or write the mrf. If the grf is overwritten,
|
||||
* we are done
|
||||
*/
|
||||
for (j = i + 1; j < p->nr_insn; ++j) {
|
||||
struct brw_instruction *inst = p->store + j;
|
||||
if (removeInst[j])
|
||||
continue;
|
||||
|
||||
if (brw_is_grf_read(inst, grf_index, simd16_size)) {
|
||||
removeInst[i] = false;
|
||||
break;
|
||||
}
|
||||
|
||||
if (brw_is_grf_straight_write(inst, grf_index))
|
||||
break;
|
||||
}
|
||||
|
||||
/* Note that with the top down traversal, we can safely pacth the mov
|
||||
* instruction
|
||||
*/
|
||||
if (removeInst[i]) {
|
||||
grf_inst->bits1.da1.dest_reg_file = mov->bits1.da1.dest_reg_file;
|
||||
grf_inst->bits1.da1.dest_reg_nr = mov->bits1.da1.dest_reg_nr;
|
||||
}
|
||||
}
|
||||
|
||||
brw_remove_inst(p, removeInst);
|
||||
free(removeInst);
|
||||
}
|
||||
|
||||
static bool
|
||||
is_single_channel_dp4(struct brw_instruction *insn)
|
||||
{
|
||||
|
||||
Reference in New Issue
Block a user