r600/sfn: rework testing readport config for more than one source
When checking the readport config for a number of sources that would be used in a multi-slot instruction, then return the index of the source for which readport allocation fails. With that we can later add a mov instruction to change the source channels configuration. In addition pass a std::array instead of a C-array to make the interface more c++-like and prepare for the next patch. Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36860>
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@@ -71,8 +71,8 @@ public:
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void visit(const UniformValue& value) override;
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};
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bool
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AluReadportReservation::schedule_vec_src(PVirtualValue src[3],
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unsigned
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AluReadportReservation::schedule_vec_src(const std::array<PVirtualValue, 3>& src,
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int nsrc,
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AluBankSwizzle swz)
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{
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@@ -90,9 +90,12 @@ AluReadportReservation::schedule_vec_src(PVirtualValue src[3],
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visitor.cycle = cycle_vec(swz, i);
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visitor.isrc = i;
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src[i]->accept(visitor);
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if (!visitor.success) {
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return i;
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}
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}
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return visitor.success;
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return nsrc;
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}
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bool
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@@ -17,7 +17,9 @@ public:
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AluReadportReservation(const AluReadportReservation& orig) = default;
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AluReadportReservation& operator=(const AluReadportReservation& orig) = default;
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bool schedule_vec_src(PVirtualValue src[3], int nsrc, AluBankSwizzle swz);
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unsigned schedule_vec_src(const std::array<PVirtualValue, 3>& src,
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int nsrc,
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AluBankSwizzle swz);
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bool schedule_vec_instruction(const AluInstr& alu, AluBankSwizzle swz);
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bool schedule_trans_instruction(const AluInstr& alu, AluBankSwizzle swz);
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@@ -711,7 +711,7 @@ AluInstr::check_readport_validation(PRegister old_src, PVirtualValue new_src) co
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assert(nsrc * m_alu_slots == m_src.size());
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for (int s = 0; s < m_alu_slots && success; ++s) {
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PVirtualValue src[3];
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std::array<PVirtualValue, 3> src;
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auto ireg = m_src.begin() + s * nsrc;
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for (unsigned i = 0; i < nsrc; ++i, ++ireg)
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@@ -720,7 +720,7 @@ AluInstr::check_readport_validation(PRegister old_src, PVirtualValue new_src) co
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AluBankSwizzle bs = alu_vec_012;
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while (bs != alu_vec_unknown) {
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AluReadportReservation rpr = rpr_sum;
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if (rpr.schedule_vec_src(src, nsrc, bs)) {
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if (rpr.schedule_vec_src(src, nsrc, bs) == nsrc) {
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rpr_sum = rpr;
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break;
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}
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@@ -877,7 +877,7 @@ AluInstr::split(ValueFactory& vf, AluGroup& group)
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assert(nsrc * m_alu_slots == m_src.size());
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for (int s = 0; s < m_alu_slots; ++s) {
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PVirtualValue src[3];
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std::array<PVirtualValue, 3> src;
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auto ireg = m_src.begin() + s * nsrc;
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for (unsigned i = 0; i < nsrc; ++i, ++ireg)
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@@ -886,7 +886,7 @@ AluInstr::split(ValueFactory& vf, AluGroup& group)
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AluBankSwizzle bs = alu_vec_012;
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while (bs != alu_vec_unknown) {
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AluReadportReservation rpr = rr;
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if (rpr.schedule_vec_src(src, nsrc, bs)) {
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if (rpr.schedule_vec_src(src, nsrc, bs) == nsrc) {
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rr = rpr;
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break;
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}
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@@ -327,16 +327,19 @@ bool AluGroup::replace_source(PRegister old_src, PVirtualValue new_src)
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auto& srcs = m_slots[slot]->sources();
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PVirtualValue test_src[3];
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std::transform(srcs.begin(), srcs.end(), test_src,
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std::array<PVirtualValue, 3> test_src;
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std::transform(srcs.begin(),
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srcs.end(),
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test_src.begin(),
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[old_src, new_src](PVirtualValue s) {
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return old_src->equal_to(*s) ? new_src : s;
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});
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return old_src->equal_to(*s) ? new_src : s;
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});
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AluBankSwizzle bs = alu_vec_012;
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while (bs != alu_vec_unknown) {
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AluReadportReservation rpr = rpr_sum;
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if (rpr.schedule_vec_src(test_src,srcs.size(), bs)) {
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unsigned nsrc = srcs.size();
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if (rpr.schedule_vec_src(test_src, nsrc, bs) == nsrc) {
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rpr_sum = rpr;
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break;
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}
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