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radeonsi: Enable tiling for depth/stencil resources.

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Enabling it for all resources still seems to cause problems, but depth/stencil
buffers are always accessed with tiling by the DB block.

Also, stick to 1D tiling for now. Getting 2D tiling to work properly will
require substantial changes in libdrm_radeon and possibly the kernel as well.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Michel Dänzer
2013-01-17 16:31:58 +01:00
committed by Michel Dänzer
parent c408f0c5c4
commit c486e3ef34
1 changed files with 3 additions and 4 deletions
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src/gallium/drivers/radeonsi/r600_texture.c
+3 -4
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@@ -521,14 +521,13 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
int r;
#if 0
if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
!(templ->bind & PIPE_BIND_SCANOUT)) {
!(templ->bind & PIPE_BIND_SCANOUT) &&
util_format_is_depth_or_stencil(templ->format)) {
if (permit_hardware_blit(screen, templ)) {
array_mode = V_009910_ARRAY_2D_TILED_THIN1;
array_mode = V_009910_ARRAY_1D_TILED_THIN1;
}
}
#endif
r = r600_init_surface(rscreen, &surface, templ, array_mode,
templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);