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bi/va: Add instructions required for KHR_shader_atomic_int64

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Add 64-bit atomic instructions for bifrost/valhall

Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Signed-off-by: Ashley Smith <ashley.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35789>
This commit is contained in:
Ashley Smith
2025-07-11 09:47:29 +01:00
committed by Marge Bot
parent 3b9a1ce4ca
commit c3a21fb0af
3 changed files with 68 additions and 3 deletions
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src/panfrost/compiler/bifrost/ISA.xml
+65
View File
@@ -8298,6 +8298,33 @@
<immediate name="sr_count" size="4" pseudo="true"/>
</ins>
<!-- Scheduler lowered to *ATOM_C.i64/+ATOM_CX. Real Valhall instructions. -->
<ins name="ATOM_RETURN.i64" pseudo="true" staging="rw=sr_count" message="atomic" unit="add">
<src start="0"/>
<src start="3"/>
<mod name="atom_opc" start="9" size="5">
<reserved/>
<reserved/>
<opt>aadd</opt>
<reserved/>
<reserved/>
<reserved/>
<reserved/>
<reserved/>
<opt>asmin</opt>
<opt>asmax</opt>
<opt>aumin</opt>
<opt>aumax</opt>
<opt>aand</opt>
<opt>aor</opt>
<opt>axor</opt>
<opt>axchg</opt> <!-- For Valhall -->
<opt>acmpxchg</opt> <!-- For Valhall -->
</mod>
<!-- not actually encoded, but used for IR -->
<immediate name="sr_count" size="4" pseudo="true"/>
</ins>
<ins name="ATOM1_RETURN.i32" pseudo="true" staging="w=sr_count" message="atomic" unit="add">
<src start="0"/>
<src start="3"/>
@@ -8310,6 +8337,20 @@
</mod>
<!-- not actually encoded, but used for IR -->
<immediate name="sr_count" size="4" pseudo="true"/>
</ins>
<ins name="ATOM1_RETURN.i64" pseudo="true" staging="w=sr_count" message="atomic" unit="add">
<src start="0"/>
<src start="3"/>
<mod name="atom_opc" start="6" size="3">
<opt>ainc</opt>
<opt>adec</opt>
<opt>aumax1</opt>
<opt>asmax1</opt>
<opt>aor1</opt>
</mod>
<!-- not actually encoded, but used for IR -->
<immediate name="sr_count" size="4" pseudo="true"/>
</ins>
<ins name="ATOM.i32" pseudo="true" staging="r=sr_count" message="atomic" unit="add">
@@ -8336,6 +8377,30 @@
<immediate name="sr_count" size="4" pseudo="true"/>
</ins>
<ins name="ATOM.i64" pseudo="true" staging="r=sr_count" message="atomic" unit="add">
<src start="0"/>
<src start="3"/>
<mod name="atom_opc" start="9" size="4">
<reserved/>
<reserved/>
<opt>aadd</opt>
<reserved/>
<reserved/>
<reserved/>
<reserved/>
<reserved/>
<opt>asmin</opt>
<opt>asmax</opt>
<opt>aumin</opt>
<opt>aumax</opt>
<opt>aand</opt>
<opt>aor</opt>
<opt>axor</opt>
</mod>
<!-- not actually encoded, but used for IR -->
<immediate name="sr_count" size="4" pseudo="true"/>
</ins>
<!-- *CUBEFACE1/+CUBEFACE2 pair, two destinations, scheduler lowered -->
<ins name="CUBEFACE" pseudo="true" dests="2" unit="add">
<src start="0"/>
src/panfrost/compiler/valhall/ISA.xml
+3
View File
@@ -2508,7 +2508,10 @@
<slot/>
<sr_count/>
<sr_write_count/>
<!-- Only valid with .xchg to implement ACMPXCHG -->
<va_mod name="compare" start="26" size="1"/>
<atom_opc/>
<va_mod name="memory_width" start="128" size="1" implied="true"/>
src/panfrost/compiler/valhall/valhall.c.py
-3
View File
@@ -57,9 +57,6 @@ SKIP = set([
"RSHIFT_OR.i64",
"LSHIFT_XOR.i64",
"RSHIFT_XOR.i64",
"ATOM.i64",
"ATOM_RETURN.i64",
"ATOM1_RETURN.i64",
# CLPER widens
"CLPER.s32",