intel/isl: Reduce halign for disabled CCS on XeHP
Reduce the space consumption of mipmapped images which don't use compression. Based on Bspec 43862 (r52666). Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29167>
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@@ -215,21 +215,39 @@ isl_gfx125_choose_image_alignment_el(const struct isl_device *dev,
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*image_align_el = tiling == ISL_TILING_LINEAR ?
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isl_extent3d(128, 4, 1) :
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isl_extent3d(16, 4, 1);
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} else {
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} else if (_isl_surf_info_supports_ccs(dev, info->format, info->usage) ||
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tiling == ISL_TILING_LINEAR) {
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/* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
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*
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* - Losslessly Compressed Surfaces Must be HALIGN=128 for all
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* supported Bpp
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* - 64bpe and 128bpe Surfaces Must Be HALIGN=64Bytes or 128Bytes (4,
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* 8 texels or 16 texels)
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* - Linear Surfaces surfaces must use HALIGN=128, including 1D which
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* is always Linear.
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*
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* Even though we could choose a horizontal alignment of 64B for certain
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* 64 and 128-bit formats, we want to be able to enable CCS whenever
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* possible and CCS requires 128B horizontal alignment.
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*/
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*image_align_el = isl_extent3d(128 * 8 / fmtl->bpb, 4, 1);
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} else if (fmtl->bpb >= 64) {
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assert(fmtl->bpb == 64 || fmtl->bpb == 128);
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/* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
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*
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* - 64bpe and 128bpe Surfaces Must Be HALIGN=64Bytes or 128Bytes (4,
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* 8 texels or 16 texels)
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*
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* HALIGN=128 is used for losslessly compressed or linear surfaces. For
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* other surface types, pick the smaller alignment of HALIGN=64 to save
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* space.
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*/
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*image_align_el = isl_extent3d(64 * 8 / fmtl->bpb, 4, 1);
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} else {
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/* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
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*
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* HALIGN=16Bytes(8 texels) is allowed only for 16b Depth, Stencil
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* Surfaces (8b) and Tiled 24bpp, 48bpp and 96bpp surfaces
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*
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* HALIGN=16 would save the most space, but it is reserved for the cases
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* handled earlier in this if-ladder. Choose the next smallest alignment
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* possible, HALIGN=32.
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*/
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*image_align_el = isl_extent3d(32 * 8 / fmtl->bpb, 4, 1);
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}
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}
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