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radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_const

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This commit is contained in:
Tom Stellard
2012-05-09 11:44:27 -04:00
parent d0403cafd4
commit c2e081030e
5 changed files with 20 additions and 38 deletions
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src/gallium/drivers/radeon/AMDGPUGenShaderPatterns.pl
-30
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@@ -1,30 +0,0 @@
#===-- AMDGPUGenShaderPatterns.pl - TODO: Add brief description -------===#
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
#===----------------------------------------------------------------------===#
#
# TODO: Add full description
#
#===----------------------------------------------------------------------===#
use strict;
use warnings;
use AMDGPUConstants;
my $reg_prefix = $ARGV[0];
for (my $i = 0; $i < CONST_REG_COUNT * 4; $i++) {
my $index = get_hw_index($i);
my $chan = get_chan_str($i);
print <<STRING;
def : Pat <
(int_AMDGPU_load_const $i),
(f32 (MOV (f32 $reg_prefix$index\_$chan)))
>;
STRING
}
src/gallium/drivers/radeon/Makefile
-3
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@@ -35,9 +35,6 @@ else
cp R600IntrinsicsOpenCL.td R600Intrinsics.td
endif
R600ShaderPatterns.td: AMDGPUGenShaderPatterns.pl
$(PERL) $^ C > $@
R600RegisterInfo.td: R600GenRegisterInfo.pl
$(PERL) $^ > $@
src/gallium/drivers/radeon/Makefile.sources
-1
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@@ -1,7 +1,6 @@
GENERATED_SOURCES := \
R600Intrinsics.td \
R600ShaderPatterns.td \
R600RegisterInfo.td \
AMDGPUInstrEnums.td \
SIRegisterInfo.td \
src/gallium/drivers/radeon/R600ISelLowering.cpp
+13 -1
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@@ -40,6 +40,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
{
MachineFunction * MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
MachineBasicBlock::iterator I = *MI;
switch (MI->getOpcode()) {
default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
@@ -89,6 +90,18 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
case AMDIL::LOCAL_SIZE_Z:
lowerImplicitParameter(MI, *BB, MRI, 8);
break;
case AMDIL::R600_LOAD_CONST:
{
int64_t RegIndex = MI->getOperand(1).getImm();
unsigned ConstantReg = AMDIL::R600_CReg32RegClass.getRegister(RegIndex);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::COPY))
.addOperand(MI->getOperand(0))
.addReg(ConstantReg);
MI->eraseFromParent();
break;
}
case AMDIL::LOAD_INPUT:
{
int64_t RegIndex = MI->getOperand(1).getImm();
@@ -99,7 +112,6 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
}
case AMDIL::STORE_OUTPUT:
{
MachineBasicBlock::iterator I = *MI;
int64_t OutputIndex = MI->getOperand(1).getImm();
unsigned OutputReg = AMDIL::R600_TReg32RegClass.getRegister(OutputIndex);
src/gallium/drivers/radeon/R600Instructions.td
+7 -3
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@@ -991,6 +991,13 @@ def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
int_r600_read_local_size_z>;
def R600_LOAD_CONST : AMDGPUShaderInst <
(outs R600_Reg32:$dst),
(ins i32imm:$src0),
"R600_LOAD_CONST $dst, $src0",
[(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
>;
def LOAD_INPUT : AMDGPUShaderInst <
(outs R600_Reg32:$dst),
(ins i32imm:$src),
@@ -1050,7 +1057,4 @@ def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
include "R600ShaderPatterns.td"
} // End isR600toCayman Predicate