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freedreno/afuc: Fix setbit/clrbit parsing

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We can't modify the instruction when parsing an operand, we will modify
the previous instruction, so just flatten out the rule.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26771>
This commit is contained in:
Connor Abbott
2023-12-18 17:25:35 -05:00
committed by Marge Bot
parent 105ea1fc68
commit c1955a0b16
1 changed files with 2 additions and 4 deletions
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src/freedreno/afuc/parser.y
+2 -4
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@@ -246,10 +246,8 @@ alu_2src_op: T_OP_ADD { new_instr(OPC_ADD); }
alu_2src_instr: alu_2src_op reg ',' reg ',' reg { dst($2); src1($4); src2($6); }
| alu_2src_op reg ',' reg ',' immediate { dst($2); src1($4); immed($6); }
alu_setbit_src2: T_BIT { bit($1); instr->opc = OPC_SETBITI; }
| reg { src2($1); }
alu_clrsetbit_instr: T_OP_SETBIT reg ',' reg ',' alu_setbit_src2 { new_instr(OPC_SETBIT); dst($2); src1($4); }
alu_clrsetbit_instr: T_OP_SETBIT reg ',' reg ',' T_BIT { new_instr(OPC_SETBITI); dst($2); src1($4); bit($6); }
| T_OP_SETBIT reg ',' reg ',' reg { new_instr(OPC_SETBIT); dst($2); src1($4); src2($6); }
| T_OP_CLRBIT reg ',' reg ',' T_BIT { new_instr(OPC_CLRBIT); dst($2); src1($4); bit($6); }
alu_bitfield_op: T_OP_UBFX { new_instr(OPC_UBFX); }