r600: implement DP2 opcode
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@@ -3017,7 +3017,14 @@ GLboolean assemble_DOT(r700_AssemblerBase *pAsm)
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return GL_FALSE;
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}
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if(OPCODE_DP3 == pAsm->pILInst[pAsm->uiCurInst].Opcode)
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if(OPCODE_DP2 == pAsm->pILInst[pAsm->uiCurInst].Opcode)
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{
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zerocomp_PVSSRC(&(pAsm->S[0].src),2);
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zerocomp_PVSSRC(&(pAsm->S[0].src),3);
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zerocomp_PVSSRC(&(pAsm->S[1].src),2);
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zerocomp_PVSSRC(&(pAsm->S[1].src),3);
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}
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else if(OPCODE_DP3 == pAsm->pILInst[pAsm->uiCurInst].Opcode)
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{
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zerocomp_PVSSRC(&(pAsm->S[0].src), 3);
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zerocomp_PVSSRC(&(pAsm->S[1].src), 3);
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@@ -5694,6 +5701,7 @@ GLboolean AssembleInstr(GLuint uiFirstInst,
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return GL_FALSE;
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break;
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case OPCODE_DP2:
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case OPCODE_DP3:
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case OPCODE_DP4:
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case OPCODE_DPH:
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@@ -6019,7 +6027,7 @@ GLboolean AssembleInstr(GLuint uiFirstInst,
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return GL_TRUE;
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default:
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radeon_error("internal: unknown instruction\n");
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radeon_error("r600: unknown instruction %d\n", pILInst[i].Opcode);
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return GL_FALSE;
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}
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}
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