amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.
Even if surface info input flag "tcComaptible" is enabled, tc compatible may be not supported if tile split happens for depth surfaces. Add a new flag in output structure to notify client to disable tc compatible in this case.
This commit is contained in:
committed by
Marek Olšák
parent
2ffb30c2af
commit
c12e35065a
@@ -534,9 +534,16 @@ typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT
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INT_32 tileIndex; ///< Tile index, MAY be "downgraded"
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INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
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/// Special information to work around SI mipmap swizzle bug UBTS #317508
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BOOL_32 last2DLevel; ///< TRUE if this is the last 2D(3D) tiled
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///< Only meaningful when create flag checkLast2DLevel is set
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/// Output flags
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struct
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{
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/// Special information to work around SI mipmap swizzle bug UBTS #317508
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UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled
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///< Only meaningful when create flag checkLast2DLevel is set
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UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible
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UINT_32 reserved :30; ///< Reserved bits
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};
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/// Stereo info
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ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE
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} ADDR_COMPUTE_SURFACE_INFO_OUTPUT;
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@@ -449,6 +449,7 @@ ADDR_E_RETURNCODE AddrLib::ComputeSurfaceInfo(
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pOut->pixelBits = localIn.bpp;
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pOut->numSamples = localIn.numSamples;
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pOut->last2DLevel = FALSE;
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pOut->tcCompatible = FALSE;
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#if !ALT_TEST
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if (localIn.numSamples > 1)
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@@ -483,7 +483,8 @@ INT_32 CiAddrLib::HwlPostCheckTileIndex(
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// tileSplitBytes stored in m_tileTable is only valid for depth entries
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if (type == ADDR_DEPTH_SAMPLE_ORDER)
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{
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if (pInfo->tileSplitBytes == m_tileTable[index].info.tileSplitBytes)
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if (Min(m_tileTable[index].info.tileSplitBytes,
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m_rowSize) == pInfo->tileSplitBytes)
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{
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break;
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}
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@@ -621,6 +622,9 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeSurfaceInfo(
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pOut->macroModeIndex = TileIndexInvalid;
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}
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// Pass tcCompatible flag from input to output; and turn off it if tile split occurs
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pOut->tcCompatible = pIn->flags.tcCompatible;
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ADDR_E_RETURNCODE retCode = SiAddrLib::HwlComputeSurfaceInfo(pIn,pOut);
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if (pOut->macroModeIndex == TileIndexNoMacroIndex)
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@@ -1010,11 +1014,18 @@ VOID CiAddrLib::HwlSetupTileInfo(
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// See table entries 0-4
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if (flags.depth || flags.stencil)
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{
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// tileSize = thickness * bpp * numSamples * 8 * 8 / 8
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UINT_32 tileSize = thickness * bpp * numSamples * 8;
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// Turn off tc compatible if row_size is smaller than tile size (tile split occurs).
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if (m_rowSize < tileSize)
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{
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flags.tcCompatible = FALSE;
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pOut->tcCompatible = FALSE;
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}
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if (flags.depth && (flags.nonSplit || flags.tcCompatible))
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{
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// tileSize = bpp * numSamples * 8 * 8 / 8
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UINT_32 tileSize = bpp * numSamples * 8;
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// Texure readable depth surface should not be split
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switch (tileSize)
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{
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@@ -1215,6 +1226,29 @@ VOID CiAddrLib::HwlSetupTileInfo(
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pOut->tileIndex = 8;
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*pTileInfo = m_tileTable[8].info;
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}
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// Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil is
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// handled at tileIndex selecting time.
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if (pOut->tcCompatible && (inTileType != ADDR_DEPTH_SAMPLE_ORDER))
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{
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if (IsMacroTiled(tileMode))
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{
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// Non-depth entries store a split factor
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UINT_32 sampleSplit = m_tileTable[pOut->tileIndex].info.tileSplitBytes;
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UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
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UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
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if (m_rowSize < colorTileSplit)
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{
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pOut->tcCompatible = FALSE;
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}
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}
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else
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{
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// Client should not enable tc compatible for linear and 1D tile modes.
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pOut->tcCompatible = FALSE;
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}
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}
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}
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/**
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@@ -1517,14 +1551,7 @@ INT_32 CiAddrLib::HwlComputeMacroModeIndex(
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pTileInfo->pipeConfig = m_tileTable[tileIndex].info.pipeConfig;
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if (m_tileTable[tileIndex].type != ADDR_DEPTH_SAMPLE_ORDER)
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{
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pTileInfo->tileSplitBytes = tileSplitC;
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}
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else
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{
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pTileInfo->tileSplitBytes = m_tileTable[tileIndex].info.tileSplitBytes;
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}
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pTileInfo->tileSplitBytes = tileSplitC;
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}
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if (NULL != pTileMode)
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