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Remove r500 stuff

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This commit is contained in:
Alex Deucher
2009-04-10 16:36:18 -04:00
parent 69edb8a156
commit c0419f190c
11 changed files with 165 additions and 2644 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/r600/Makefile
-2
View File
@@ -51,8 +51,6 @@ DRIVER_SOURCES = \
r600_fragprog.c \
r600_fragprog_swizzle.c \
r600_fragprog_emit.c \
r700_fragprog.c \
r700_fragprog_emit.c \
r600_shader.c \
r600_emit.c \
r600_swtcl.c \
src/mesa/drivers/dri/r600/r600_cmdbuf.c
+54 -186
View File
@@ -75,7 +75,6 @@ static unsigned packet0_count(r600ContextPtr r600, uint32_t *pkt)
}
#define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
#define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
{
@@ -121,48 +120,6 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
}
}
void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
{
r600ContextPtr r600 = R600_CONTEXT(ctx);
BATCH_LOCALS(&r600->radeon);
drm_r300_cmd_header_t cmd;
uint32_t addr, ndw, i, sz;
int type, clamp, stride;
if (!r600->radeon.radeonScreen->kernel_mm) {
uint32_t dwords;
dwords = (*atom->check) (ctx, atom);
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_BATCH_TABLE(atom->cmd, dwords);
END_BATCH();
return;
}
cmd.u = atom->cmd[0];
sz = cmd.r500fp.count;
addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
addr |= (type << 16);
addr |= (clamp << 17);
stride = type ? 4 : 6;
ndw = sz * stride;
if (ndw) {
BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
OUT_BATCH(addr);
OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
for (i = 0; i < ndw; i++) {
OUT_BATCH(atom->cmd[i+1]);
}
END_BATCH();
}
}
static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
{
r600ContextPtr r600 = R600_CONTEXT(ctx);
@@ -332,22 +289,6 @@ int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
return cnt ? (cnt * 4) + 1 : 0;
}
int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
{
int cnt;
cnt = r500fp_count(atom->cmd);
return cnt ? (cnt * 6) + 1 : 0;
}
int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
{
int cnt;
cnt = r500fp_count(atom->cmd);
return cnt ? (cnt * 4) + 1 : 0;
}
#define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
do { \
r600->hw.ATOM.cmd_size = (SZ); \
@@ -366,16 +307,8 @@ int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
void r600InitCmdBuf(r600ContextPtr r600)
{
int mtu;
int has_tcl = 1;
int is_r500 = 0;
int i;
if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
has_tcl = 0;
if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
is_r500 = 1;
r600->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
mtu = r600->radeon.glCtx->Const.MaxTextureUnits;
@@ -394,11 +327,7 @@ void r600InitCmdBuf(r600ContextPtr r600)
r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_STATE_FLUSH_REG, 1);
r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH_1] = 0;
r600->hw.vap_cntl.cmd[R600_VAP_CNTL_CMD] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL, 1);
if (is_r500) {
ALLOC_STATE(vap_index_offset, always, 2, 0);
r600->hw.vap_index_offset.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
r600->hw.vap_index_offset.cmd[1] = 0;
}
ALLOC_STATE(vte, always, 3, 0);
r600->hw.vte.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VTE_CNTL, 2);
ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
@@ -416,24 +345,20 @@ void r600InitCmdBuf(r600ContextPtr r600)
ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
r600->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
if (has_tcl) {
ALLOC_STATE(vap_clip_cntl, always, 2, 0);
r600->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CLIP_CNTL, 1);
ALLOC_STATE(vap_clip, always, 5, 0);
r600->hw.vap_clip.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_GB_VERT_CLIP_ADJ, 4);
ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
r600->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
}
ALLOC_STATE(vap_clip_cntl, always, 2, 0);
r600->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CLIP_CNTL, 1);
ALLOC_STATE(vap_clip, always, 5, 0);
r600->hw.vap_clip.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_GB_VERT_CLIP_ADJ, 4);
ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
r600->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
ALLOC_STATE(vof, always, R600_VOF_CMDSIZE, 0);
r600->hw.vof.cmd[R600_VOF_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_VAP_OUTPUT_VTX_FMT_0, 2);
if (has_tcl) {
ALLOC_STATE(pvs, always, R600_PVS_CMDSIZE, 0);
r600->hw.pvs.cmd[R600_PVS_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_CODE_CNTL_0, 3);
}
ALLOC_STATE(pvs, always, R600_PVS_CMDSIZE, 0);
r600->hw.pvs.cmd[R600_PVS_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_CODE_CNTL_0, 3);
ALLOC_STATE(gb_enable, always, 2, 0);
r600->hw.gb_enable.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_ENABLE, 1);
@@ -472,24 +397,12 @@ void r600InitCmdBuf(r600ContextPtr r600)
r600->hw.su_depth_scale.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_DEPTH_SCALE, 2);
ALLOC_STATE(rc, always, R600_RC_CMDSIZE, 0);
r600->hw.rc.cmd[R600_RC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_COUNT, 2);
if (is_r500) {
ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_IP_0, 16);
for (i = 0; i < 8; i++) {
r600->hw.ri.cmd[R600_RI_CMD_0 + i +1] =
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
}
ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0);
r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_INST_0, 1);
} else {
ALLOC_STATE(ri, always, R600_RI_CMDSIZE, 0);
r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_IP_0, 8);
ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0);
r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_INST_0, 1);
}
ALLOC_STATE(ri, always, R600_RI_CMDSIZE, 0);
r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_IP_0, 8);
ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0);
r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_INST_0, 1);
ALLOC_STATE(sc_hyperz, always, 3, 0);
r600->hw.sc_hyperz.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_HYPERZ, 2);
ALLOC_STATE(sc_screendoor, always, 2, 0);
@@ -497,41 +410,24 @@ void r600InitCmdBuf(r600ContextPtr r600)
ALLOC_STATE(us_out_fmt, always, 6, 0);
r600->hw.us_out_fmt.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_OUT_FMT, 5);
if (is_r500) {
ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
r600->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_US_CONFIG, 2);
r600->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
r600->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
r600->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r600->radeon.radeonScreen, R500_US_FC_CTRL, 1);
r600->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
ALLOC_STATE(fp, always, R600_FP_CMDSIZE, 0);
r600->hw.fp.cmd[R600_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CONFIG, 3);
r600->hw.fp.cmd[R600_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CODE_ADDR_0, 4);
ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
r600->hw.r500fp.cmd[R600_FPI_CMD_0] =
cmdr500fp(r600->radeon.radeonScreen, 0, 0, 0, 0);
r600->hw.r500fp.emit = emit_r500fp;
ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
r600->hw.r500fp_const.cmd[R600_FPI_CMD_0] =
cmdr500fp(r600->radeon.radeonScreen, 0, 0, 1, 0);
r600->hw.r500fp_const.emit = emit_r500fp;
} else {
ALLOC_STATE(fp, always, R600_FP_CMDSIZE, 0);
r600->hw.fp.cmd[R600_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CONFIG, 3);
r600->hw.fp.cmd[R600_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CODE_ADDR_0, 4);
ALLOC_STATE(fpt, variable, R600_FPT_CMDSIZE, 0);
r600->hw.fpt.cmd[R600_FPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_TEX_INST_0, 0);
ALLOC_STATE(fpt, variable, R600_FPT_CMDSIZE, 0);
r600->hw.fpt.cmd[R600_FPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_TEX_INST_0, 0);
ALLOC_STATE(fpi[0], variable, R600_FPI_CMDSIZE, 0);
r600->hw.fpi[0].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_INST_0, 1);
ALLOC_STATE(fpi[1], variable, R600_FPI_CMDSIZE, 1);
r600->hw.fpi[1].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_ADDR_0, 1);
ALLOC_STATE(fpi[2], variable, R600_FPI_CMDSIZE, 2);
r600->hw.fpi[2].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_INST_0, 1);
ALLOC_STATE(fpi[3], variable, R600_FPI_CMDSIZE, 3);
r600->hw.fpi[3].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_ADDR_0, 1);
ALLOC_STATE(fpp, variable, R600_FPP_CMDSIZE, 0);
r600->hw.fpp.cmd[R600_FPP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_PFS_PARAM_0_X, 0);
ALLOC_STATE(fpi[0], variable, R600_FPI_CMDSIZE, 0);
r600->hw.fpi[0].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_INST_0, 1);
ALLOC_STATE(fpi[1], variable, R600_FPI_CMDSIZE, 1);
r600->hw.fpi[1].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_ADDR_0, 1);
ALLOC_STATE(fpi[2], variable, R600_FPI_CMDSIZE, 2);
r600->hw.fpi[2].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_INST_0, 1);
ALLOC_STATE(fpi[3], variable, R600_FPI_CMDSIZE, 3);
r600->hw.fpi[3].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_ADDR_0, 1);
ALLOC_STATE(fpp, variable, R600_FPP_CMDSIZE, 0);
r600->hw.fpp.cmd[R600_FPP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_PFS_PARAM_0_X, 0);
}
ALLOC_STATE(fogs, always, R600_FOGS_CMDSIZE, 0);
r600->hw.fogs.cmd[R600_FOGS_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_BLEND, 1);
ALLOC_STATE(fogc, always, R600_FOGC_CMDSIZE, 0);
@@ -546,13 +442,10 @@ void r600InitCmdBuf(r600ContextPtr r600)
r600->hw.bld.cmd[R600_BLD_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CBLEND, 2);
ALLOC_STATE(cmk, always, R600_CMK_CMDSIZE, 0);
r600->hw.cmk.cmd[R600_CMK_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
if (is_r500) {
ALLOC_STATE(blend_color, always, 3, 0);
r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
} else {
ALLOC_STATE(blend_color, always, 2, 0);
r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_BLEND_COLOR, 1);
}
ALLOC_STATE(blend_color, always, 2, 0);
r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_BLEND_COLOR, 1);
ALLOC_STATE(rop, always, 2, 0);
r600->hw.rop.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_ROPCNTL, 1);
ALLOC_STATE(cb, always, R600_CB_CMDSIZE, 0);
@@ -561,8 +454,7 @@ void r600InitCmdBuf(r600ContextPtr r600)
r600->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_DITHER_CTL, 9);
ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
r600->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_AARESOLVE_CTL, 1);
ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
ALLOC_STATE(zs, always, R600_ZS_CMDSIZE, 0);
r600->hw.zs.cmd[R600_ZS_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_ZB_CNTL, 3);
@@ -583,51 +475,27 @@ void r600InitCmdBuf(r600ContextPtr r600)
ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
r600->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_PITCH, 1);
/* VPU only on TCL */
if (has_tcl) {
int i;
ALLOC_STATE(vpi, vpu, R600_VPI_CMDSIZE, 0);
r600->hw.vpi.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R600_PVS_CODE_START, 0);
r600->hw.vpi.emit = emit_vpu;
ALLOC_STATE(vpi, vpu, R600_VPI_CMDSIZE, 0);
r600->hw.vpi.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R600_PVS_CODE_START, 0);
r600->hw.vpi.emit = emit_vpu;
if (is_r500) {
ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0);
r600->hw.vpp.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R500_PVS_CONST_START, 0);
r600->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0);
r600->hw.vpp.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R600_PVS_CONST_START, 0);
r600->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0);
r600->hw.vps.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
r600->hw.vps.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0);
r600->hw.vps.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R600_POINT_VPORT_SCALE_OFFSET, 1);
r600->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0);
r600->hw.vpucp[i].cmd[0] =
cmdvpu(r600->radeon.radeonScreen,
R500_PVS_UCP_START + i, 1);
r600->hw.vpucp[i].emit = emit_vpu;
}
} else {
ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0);
r600->hw.vpp.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R600_PVS_CONST_START, 0);
r600->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0);
r600->hw.vps.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R600_POINT_VPORT_SCALE_OFFSET, 1);
r600->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0);
r600->hw.vpucp[i].cmd[0] =
cmdvpu(r600->radeon.radeonScreen,
R600_PVS_UCP_START + i, 1);
r600->hw.vpucp[i].emit = emit_vpu;
}
}
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0);
r600->hw.vpucp[i].cmd[0] =
cmdvpu(r600->radeon.radeonScreen,
R600_PVS_UCP_START + i, 1);
r600->hw.vpucp[i].emit = emit_vpu;
}
/* Textures */
src/mesa/drivers/dri/r600/r600_context.c
+11 -15
View File
@@ -345,10 +345,8 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual,
ctx->Const.MaxTextureMaxAnisotropy = 16.0;
ctx->Const.MaxTextureLodBias = 16.0;
if (screen->chip_family >= CHIP_FAMILY_RV515) {
ctx->Const.MaxTextureLevels = 13;
ctx->Const.MaxTextureRectSize = 4096;
}
ctx->Const.MaxTextureLevels = 13;
ctx->Const.MaxTextureRectSize = 4096;
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
@@ -394,17 +392,15 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual,
_tnl_allow_vertex_fog(ctx, GL_TRUE);
/* currently bogus data */
if (screen->chip_flags & RADEON_CHIPSET_TCL) {
ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
ctx->Const.VertexProgram.MaxNativeInstructions =
VSF_MAX_FRAGMENT_LENGTH / 4;
ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
ctx->Const.VertexProgram.MaxTemps = 32;
ctx->Const.VertexProgram.MaxNativeTemps =
/*VSF_MAX_FRAGMENT_TEMPS */ 32;
ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */
ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
}
ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
ctx->Const.VertexProgram.MaxNativeInstructions =
VSF_MAX_FRAGMENT_LENGTH / 4;
ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
ctx->Const.VertexProgram.MaxTemps = 32;
ctx->Const.VertexProgram.MaxNativeTemps =
/*VSF_MAX_FRAGMENT_TEMPS */ 32;
ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */
ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
ctx->Const.FragmentProgram.MaxNativeTemps = PFS_NUM_TEMP_REGS;
ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */
src/mesa/drivers/dri/r600/r600_ioctl.c
+51 -153
View File
@@ -215,16 +215,8 @@ static void r600EmitClearState(GLcontext * ctx)
BATCH_LOCALS(&r600->radeon);
__DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
int i;
int has_tcl = 1;
int is_r500 = 0;
GLuint vap_cntl;
if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
has_tcl = 0;
if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
is_r500 = 1;
/* State atom dirty tracking is a little subtle here.
*
* On the one hand, we need to make sure base state is emitted
@@ -243,12 +235,9 @@ static void r600EmitClearState(GLcontext * ctx)
*/
BEGIN_BATCH(31);
OUT_BATCH_REGSEQ(R600_VAP_PROG_STREAM_CNTL_0, 1);
if (!has_tcl)
OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) |
((R600_LAST_VEC | (2 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT)));
else
OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) |
((R600_LAST_VEC | (1 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT)));
OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) |
((R600_LAST_VEC | (1 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT)));
OUT_BATCH_REGVAL(R600_FG_FOG_BLEND, 0);
OUT_BATCH_REGVAL(R600_VAP_PROG_STREAM_CNTL_EXT_0,
@@ -314,13 +303,11 @@ static void r600EmitClearState(GLcontext * ctx)
R600_STATECHANGE(r600, bld);
R600_STATECHANGE(r600, ps);
if (has_tcl) {
R600_STATECHANGE(r600, vap_clip_cntl);
R600_STATECHANGE(r600, vap_clip_cntl);
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH_REGVAL(R600_VAP_CLIP_CNTL, R600_PS_UCP_MODE_CLIP_AS_TRIFAN | R600_CLIP_DISABLE);
END_BATCH();
}
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH_REGVAL(R600_VAP_CLIP_CNTL, R600_PS_UCP_MODE_CLIP_AS_TRIFAN | R600_CLIP_DISABLE);
END_BATCH();
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH_REGVAL(R600_GA_POINT_SIZE,
@@ -328,146 +315,57 @@ static void r600EmitClearState(GLcontext * ctx)
((dPriv->h * 6) << R600_POINTSIZE_Y_SHIFT));
END_BATCH();
if (!is_r500) {
R600_STATECHANGE(r600, ri);
R600_STATECHANGE(r600, rc);
R600_STATECHANGE(r600, rr);
BEGIN_BATCH(14);
OUT_BATCH_REGSEQ(R600_RS_IP_0, 8);
for (i = 0; i < 8; ++i)
OUT_BATCH(R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3));
R600_STATECHANGE(r600, ri);
R600_STATECHANGE(r600, rc);
R600_STATECHANGE(r600, rr);
OUT_BATCH_REGSEQ(R600_RS_COUNT, 2);
OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN);
OUT_BATCH(0x0);
BEGIN_BATCH(14);
OUT_BATCH_REGSEQ(R600_RS_IP_0, 8);
for (i = 0; i < 8; ++i)
OUT_BATCH(R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3));
OUT_BATCH_REGVAL(R600_RS_INST_0, R600_RS_INST_COL_CN_WRITE);
END_BATCH();
} else {
R600_STATECHANGE(r600, ri);
R600_STATECHANGE(r600, rc);
R600_STATECHANGE(r600, rr);
OUT_BATCH_REGSEQ(R600_RS_COUNT, 2);
OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN);
OUT_BATCH(0x0);
BEGIN_BATCH(14);
OUT_BATCH_REGSEQ(R500_RS_IP_0, 8);
for (i = 0; i < 8; ++i) {
OUT_BATCH((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
}
OUT_BATCH_REGVAL(R600_RS_INST_0, R600_RS_INST_COL_CN_WRITE);
END_BATCH();
OUT_BATCH_REGSEQ(R600_RS_COUNT, 2);
OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN);
OUT_BATCH(0x0);
R600_STATECHANGE(r600, fp);
R600_STATECHANGE(r600, fpi[0]);
R600_STATECHANGE(r600, fpi[1]);
R600_STATECHANGE(r600, fpi[2]);
R600_STATECHANGE(r600, fpi[3]);
OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
END_BATCH();
}
BEGIN_BATCH(17);
OUT_BATCH_REGSEQ(R600_US_CONFIG, 3);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH_REGSEQ(R600_US_CODE_ADDR_0, 4);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH(R600_RGBA_OUT);
if (!is_r500) {
R600_STATECHANGE(r600, fp);
R600_STATECHANGE(r600, fpi[0]);
R600_STATECHANGE(r600, fpi[1]);
R600_STATECHANGE(r600, fpi[2]);
R600_STATECHANGE(r600, fpi[3]);
BEGIN_BATCH(17);
OUT_BATCH_REGSEQ(R600_US_CONFIG, 3);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH_REGSEQ(R600_US_CODE_ADDR_0, 4);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH(R600_RGBA_OUT);
OUT_BATCH_REGVAL(R600_US_ALU_RGB_INST_0,
FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
OUT_BATCH_REGVAL(R600_US_ALU_RGB_ADDR_0,
FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_INST_0,
FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_ADDR_0,
FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
END_BATCH();
} else {
struct radeon_state_atom r500fp;
uint32_t _cmd[10];
R600_STATECHANGE(r600, fp);
R600_STATECHANGE(r600, r500fp);
BEGIN_BATCH(7);
OUT_BATCH_REGSEQ(R500_US_CONFIG, 2);
OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
OUT_BATCH(0x0);
OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0));
END_BATCH();
r500fp.check = check_r500fp;
r500fp.cmd = _cmd;
r500fp.cmd[0] = cmdr500fp(r600->radeon.radeonScreen, 0, 1, 0, 0);
r500fp.cmd[1] = R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
R500_INST_RGB_OMASK_R |
R500_INST_RGB_OMASK_G |
R500_INST_RGB_OMASK_B |
R500_INST_ALPHA_OMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP;
r500fp.cmd[2] = R500_RGB_ADDR0(0) |
R500_RGB_ADDR1(0) |
R500_RGB_ADDR1_CONST |
R500_RGB_ADDR2(0) |
R500_RGB_ADDR2_CONST;
r500fp.cmd[3] = R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR1(0) |
R500_ALPHA_ADDR1_CONST |
R500_ALPHA_ADDR2(0) |
R500_ALPHA_ADDR2_CONST;
r500fp.cmd[4] = R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B |
R500_ALU_RGB_SEL_B_SRC0 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_B_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_B;
r500fp.cmd[5] = R500_ALPHA_OP_CMP |
R500_ALPHA_SWIZ_A_A |
R500_ALPHA_SWIZ_B_A;
r500fp.cmd[6] = R500_ALU_RGBA_OP_CMP |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
R500_ALU_RGBA_B_SWIZ_0 |
R500_ALU_RGBA_A_SWIZ_0;
r500fp.cmd[7] = 0;
emit_r500fp(ctx, &r500fp);
}
OUT_BATCH_REGVAL(R600_US_ALU_RGB_INST_0,
FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
OUT_BATCH_REGVAL(R600_US_ALU_RGB_ADDR_0,
FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_INST_0,
FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_ADDR_0,
FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
END_BATCH();
BEGIN_BATCH(2);
OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0);
END_BATCH();
if (has_tcl) {
vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) |
(5 << R600_PVS_NUM_CNTLRS_SHIFT) |
(12 << R600_VF_MAX_VTX_NUM_SHIFT));
if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
vap_cntl |= R500_TCL_STATE_OPTIMIZATION;
} else {
vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) |
(5 << R600_PVS_NUM_CNTLRS_SHIFT) |
(5 << R600_VF_MAX_VTX_NUM_SHIFT));
}
vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) |
(5 << R600_PVS_NUM_CNTLRS_SHIFT) |
(12 << R600_VF_MAX_VTX_NUM_SHIFT));
if (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
vap_cntl |= (2 << R600_PVS_NUM_FPUS_SHIFT);
@@ -490,9 +388,9 @@ static void r600EmitClearState(GLcontext * ctx)
OUT_BATCH_REGVAL(R600_VAP_CNTL, vap_cntl);
END_BATCH();
if (has_tcl) {
struct radeon_state_atom vpu;
uint32_t _cmd[10];
{
struct radeon_state_atom vpu;
uint32_t _cmd[10];
R600_STATECHANGE(r600, pvs);
R600_STATECHANGE(r600, vpi);
@@ -542,7 +440,7 @@ static void r600EmitClearState(GLcontext * ctx)
}
static void r600KernelClear(GLcontext *ctx, GLuint flags)
{
{
r600ContextPtr r600 = R600_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
struct radeon_framebuffer *rfb = dPriv->driverPrivate;
@@ -566,7 +464,7 @@ static void r600KernelClear(GLcontext *ctx, GLuint flags)
r600ClearBuffer(r600, CLEARBUFFER_COLOR, rrb, NULL);
bits = 0;
}
if (flags & BUFFER_BIT_FRONT_LEFT) {
rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
r600ClearBuffer(r600, bits | CLEARBUFFER_COLOR, rrb, rrbd);
src/mesa/drivers/dri/r600/r600_reg.h
-801
View File
@@ -75,7 +75,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_VF_MAX_VTX_NUM_SHIFT 18
# define R600_GL_CLIP_SPACE_DEF (0 << 22)
# define R600_DX_CLIP_SPACE_DEF (1 << 22)
# define R500_TCL_STATE_OPTIMIZATION (1 << 23)
/* This register is written directly and also starts data section
* in many 3d CP_PACKET3's
@@ -112,7 +111,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* number of vertices */
# define R600_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
#define R500_VAP_INDEX_OFFSET 0x208c
#define R600_VAP_OUTPUT_VTX_FMT_0 0x2090
# define R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
@@ -365,17 +363,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#define R600_VAP_PVS_VECTOR_INDX_REG 0x2200
# define R600_PVS_CODE_START 0
# define R600_MAX_PVS_CODE_LINES 256
# define R500_MAX_PVS_CODE_LINES 1024
# define R600_PVS_CONST_START 512
# define R500_PVS_CONST_START 1024
# define R600_MAX_PVS_CONST_VECS 256
# define R500_MAX_PVS_CONST_VECS 1024
# define R600_PVS_UCP_START 1024
# define R500_PVS_UCP_START 1536
# define R600_POINT_VPORT_SCALE_OFFSET 1030
# define R500_POINT_VPORT_SCALE_OFFSET 1542
# define R600_POINT_GEN_TEX_OFFSET 1031
# define R500_POINT_GEN_TEX_OFFSET 1543
/*
* These are obsolete defines form r600_context.h, but they might give some
@@ -423,8 +415,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_CLIP_DISABLE (1 << 16)
# define R600_UCP_CULL_ONLY_ENABLE (1 << 17)
# define R600_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18)
# define R500_COLOR2_IS_TEXTURE (1 << 20)
# define R500_COLOR3_IS_TEXTURE (1 << 21)
/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
* plane is per-pixel and the second plane is per-vertex.
@@ -703,39 +693,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_SHIFT 18
# define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_MASK 0x00fc0000
/* This table specifies the source location and format for up to 16 texture
* addresses (i[0]:i[15]) and four colors (c[0]:c[3])
*/
#define R500_RS_IP_0 0x4074
#define R500_RS_IP_1 0x4078
#define R500_RS_IP_2 0x407C
#define R500_RS_IP_3 0x4080
#define R500_RS_IP_4 0x4084
#define R500_RS_IP_5 0x4088
#define R500_RS_IP_6 0x408C
#define R500_RS_IP_7 0x4090
#define R500_RS_IP_8 0x4094
#define R500_RS_IP_9 0x4098
#define R500_RS_IP_10 0x409C
#define R500_RS_IP_11 0x40A0
#define R500_RS_IP_12 0x40A4
#define R500_RS_IP_13 0x40A8
#define R500_RS_IP_14 0x40AC
#define R500_RS_IP_15 0x40B0
#define R500_RS_IP_PTR_K0 62
#define R500_RS_IP_PTR_K1 63
#define R500_RS_IP_TEX_PTR_S_SHIFT 0
#define R500_RS_IP_TEX_PTR_T_SHIFT 6
#define R500_RS_IP_TEX_PTR_R_SHIFT 12
#define R500_RS_IP_TEX_PTR_Q_SHIFT 18
#define R500_RS_IP_COL_PTR_SHIFT 24
#define R500_RS_IP_COL_FMT_SHIFT 27
# define R500_RS_COL_PTR(x) ((x) << 24)
# define R500_RS_COL_FMT(x) ((x) << 27)
/* gap */
#define R500_RS_IP_OFFSET_DIS (0 << 31)
#define R500_RS_IP_OFFSET_EN (1 << 31)
/* gap */
/* Zero to flush caches. */
@@ -761,14 +718,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_TX_ENABLE_14 (1 << 14)
# define R600_TX_ENABLE_15 (1 << 15)
#define R500_TX_FILTER_4 0x4110
# define R500_TX_WEIGHT_1_SHIFT (0)
# define R500_TX_WEIGHT_0_SHIFT (11)
# define R500_TX_WEIGHT_PAIR (1<<22)
# define R500_TX_PHASE_SHIFT (23)
# define R500_TX_DIRECTION_HORIZONTAL (0<<27)
# define R500_TX_DIRECTION_VERITCAL (1<<27)
/* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */
#define R600_GA_POINT_S0 0x4200
@@ -802,18 +751,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_POINTSIZE_X_MASK 0xffff0000
# define R600_POINTSIZE_MAX (R600_POINTSIZE_Y_MASK / 6)
/* Blue fill color */
#define R500_GA_FILL_R 0x4220
/* Blue fill color */
#define R500_GA_FILL_G 0x4224
/* Blue fill color */
#define R500_GA_FILL_B 0x4228
/* Alpha fill color */
#define R500_GA_FILL_A 0x422c
/* Specifies maximum and minimum point & sprite sizes for per vertex size
* specification. The lower part (15:0) is MIN and (31:16) is max.
@@ -840,8 +777,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_GA_LINE_CNTL_END_TYPE_VER (1 << 16)
# define R600_GA_LINE_CNTL_END_TYPE_SQR (2 << 16) /* horizontal or vertical depending upon slope */
# define R600_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */
# define R500_GA_LINE_CNTL_SORT_NO (0 << 18)
# define R500_GA_LINE_CNTL_SORT_MINX_MINY (1 << 18)
/** TODO: looks wrong */
# define R600_LINESIZE_MAX (R600_GA_LINE_CNTL_WIDTH_MASK / 6)
/** TODO: looks wrong */
@@ -857,108 +792,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2
# define R600_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK 0xfffffffc
/* Used to load US instructions and constants */
#define R500_GA_US_VECTOR_INDEX 0x4250
# define R500_GA_US_VECTOR_INDEX_SHIFT 0
# define R500_GA_US_VECTOR_INDEX_MASK 0x000000ff
# define R500_GA_US_VECTOR_INDEX_TYPE_INSTR (0 << 16)
# define R500_GA_US_VECTOR_INDEX_TYPE_CONST (1 << 16)
# define R500_GA_US_VECTOR_INDEX_CLAMP_NO (0 << 17)
# define R500_GA_US_VECTOR_INDEX_CLAMP_CONST (1 << 17)
/* Data register for loading US instructions and constants */
#define R500_GA_US_VECTOR_DATA 0x4254
/* Specifies color properties and mappings of textures. */
#define R500_GA_COLOR_CONTROL_PS3 0x4258
# define R500_TEX0_SHADING_PS3_SOLID (0 << 0)
# define R500_TEX0_SHADING_PS3_FLAT (1 << 0)
# define R500_TEX0_SHADING_PS3_GOURAUD (2 << 0)
# define R500_TEX1_SHADING_PS3_SOLID (0 << 2)
# define R500_TEX1_SHADING_PS3_FLAT (1 << 2)
# define R500_TEX1_SHADING_PS3_GOURAUD (2 << 2)
# define R500_TEX2_SHADING_PS3_SOLID (0 << 4)
# define R500_TEX2_SHADING_PS3_FLAT (1 << 4)
# define R500_TEX2_SHADING_PS3_GOURAUD (2 << 4)
# define R500_TEX3_SHADING_PS3_SOLID (0 << 6)
# define R500_TEX3_SHADING_PS3_FLAT (1 << 6)
# define R500_TEX3_SHADING_PS3_GOURAUD (2 << 6)
# define R500_TEX4_SHADING_PS3_SOLID (0 << 8)
# define R500_TEX4_SHADING_PS3_FLAT (1 << 8)
# define R500_TEX4_SHADING_PS3_GOURAUD (2 << 8)
# define R500_TEX5_SHADING_PS3_SOLID (0 << 10)
# define R500_TEX5_SHADING_PS3_FLAT (1 << 10)
# define R500_TEX5_SHADING_PS3_GOURAUD (2 << 10)
# define R500_TEX6_SHADING_PS3_SOLID (0 << 12)
# define R500_TEX6_SHADING_PS3_FLAT (1 << 12)
# define R500_TEX6_SHADING_PS3_GOURAUD (2 << 12)
# define R500_TEX7_SHADING_PS3_SOLID (0 << 14)
# define R500_TEX7_SHADING_PS3_FLAT (1 << 14)
# define R500_TEX7_SHADING_PS3_GOURAUD (2 << 14)
# define R500_TEX8_SHADING_PS3_SOLID (0 << 16)
# define R500_TEX8_SHADING_PS3_FLAT (1 << 16)
# define R500_TEX8_SHADING_PS3_GOURAUD (2 << 16)
# define R500_TEX9_SHADING_PS3_SOLID (0 << 18)
# define R500_TEX9_SHADING_PS3_FLAT (1 << 18)
# define R500_TEX9_SHADING_PS3_GOURAUD (2 << 18)
# define R500_TEX10_SHADING_PS3_SOLID (0 << 20)
# define R500_TEX10_SHADING_PS3_FLAT (1 << 20)
# define R500_TEX10_SHADING_PS3_GOURAUD (2 << 20)
# define R500_COLOR0_TEX_OVERRIDE_NO (0 << 22)
# define R500_COLOR0_TEX_OVERRIDE_TEX_0 (1 << 22)
# define R500_COLOR0_TEX_OVERRIDE_TEX_1 (2 << 22)
# define R500_COLOR0_TEX_OVERRIDE_TEX_2 (3 << 22)
# define R500_COLOR0_TEX_OVERRIDE_TEX_3 (4 << 22)
# define R500_COLOR0_TEX_OVERRIDE_TEX_4 (5 << 22)
# define R500_COLOR0_TEX_OVERRIDE_TEX_5 (6 << 22)
# define R500_COLOR0_TEX_OVERRIDE_TEX_6 (7 << 22)
# define R500_COLOR0_TEX_OVERRIDE_TEX_7 (8 << 22)
# define R500_COLOR0_TEX_OVERRIDE_TEX_8_C2 (9 << 22)
# define R500_COLOR0_TEX_OVERRIDE_TEX_9_C3 (10 << 22)
# define R500_COLOR1_TEX_OVERRIDE_NO (0 << 26)
# define R500_COLOR1_TEX_OVERRIDE_TEX_0 (1 << 26)
# define R500_COLOR1_TEX_OVERRIDE_TEX_1 (2 << 26)
# define R500_COLOR1_TEX_OVERRIDE_TEX_2 (3 << 26)
# define R500_COLOR1_TEX_OVERRIDE_TEX_3 (4 << 26)
# define R500_COLOR1_TEX_OVERRIDE_TEX_4 (5 << 26)
# define R500_COLOR1_TEX_OVERRIDE_TEX_5 (6 << 26)
# define R500_COLOR1_TEX_OVERRIDE_TEX_6 (7 << 26)
# define R500_COLOR1_TEX_OVERRIDE_TEX_7 (8 << 26)
# define R500_COLOR1_TEX_OVERRIDE_TEX_8_C2 (9 << 26)
# define R500_COLOR1_TEX_OVERRIDE_TEX_9_C3 (10 << 26)
/* Returns idle status of various G3D block, captured when GA_IDLE written or
* when hard or soft reset asserted.
*/
#define R500_GA_IDLE 0x425c
# define R500_GA_IDLE_PIPE3_Z_IDLE (0 << 0)
# define R500_GA_IDLE_PIPE2_Z_IDLE (0 << 1)
# define R500_GA_IDLE_PIPE3_CD_IDLE (0 << 2)
# define R500_GA_IDLE_PIPE2_CD_IDLE (0 << 3)
# define R500_GA_IDLE_PIPE3_FG_IDLE (0 << 4)
# define R500_GA_IDLE_PIPE2_FG_IDLE (0 << 5)
# define R500_GA_IDLE_PIPE3_US_IDLE (0 << 6)
# define R500_GA_IDLE_PIPE2_US_IDLE (0 << 7)
# define R500_GA_IDLE_PIPE3_SC_IDLE (0 << 8)
# define R500_GA_IDLE_PIPE2_SC_IDLE (0 << 9)
# define R500_GA_IDLE_PIPE3_RS_IDLE (0 << 10)
# define R500_GA_IDLE_PIPE2_RS_IDLE (0 << 11)
# define R500_GA_IDLE_PIPE1_Z_IDLE (0 << 12)
# define R500_GA_IDLE_PIPE0_Z_IDLE (0 << 13)
# define R500_GA_IDLE_PIPE1_CD_IDLE (0 << 14)
# define R500_GA_IDLE_PIPE0_CD_IDLE (0 << 15)
# define R500_GA_IDLE_PIPE1_FG_IDLE (0 << 16)
# define R500_GA_IDLE_PIPE0_FG_IDLE (0 << 17)
# define R500_GA_IDLE_PIPE1_US_IDLE (0 << 18)
# define R500_GA_IDLE_PIPE0_US_IDLE (0 << 19)
# define R500_GA_IDLE_PIPE1_SC_IDLE (0 << 20)
# define R500_GA_IDLE_PIPE0_SC_IDLE (0 << 21)
# define R500_GA_IDLE_PIPE1_RS_IDLE (0 << 22)
# define R500_GA_IDLE_PIPE0_RS_IDLE (0 << 23)
# define R500_GA_IDLE_SU_IDLE (0 << 24)
# define R500_GA_IDLE_GA_IDLE (0 << 25)
# define R500_GA_IDLE_GA_UNIT2_IDLE (0 << 26)
/* Current value of stipple accumulator. */
#define R600_GA_LINE_STIPPLE_VALUE 0x4260
@@ -967,25 +800,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA) */
#define R600_GA_LINE_S1 0x4268
/* GA Input fifo high water marks */
#define R500_GA_FIFO_CNTL 0x4270
# define R500_GA_FIFO_CNTL_VERTEX_FIFO_MASK 0x00000007
# define R500_GA_FIFO_CNTL_VERTEX_FIFO_SHIFT 0
# define R500_GA_FIFO_CNTL_VERTEX_INDEX_MASK 0x00000038
# define R500_GA_FIFO_CNTL_VERTEX_INDEX_SHIFT 3
# define R500_GA_FIFO_CNTL_VERTEX_REG_MASK 0x00003fc0
# define R500_GA_FIFO_CNTL_VERTEX_REG_SHIFT 6
/* GA enhance/tweaks */
#define R600_GA_ENHANCE 0x4274
# define R600_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT (0 << 0)
# define R600_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */
# define R600_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT (0 << 1)
# define R600_GA_ENHANCE_FASTSYNC_CNTL_ENABLE (1 << 1) /* Enables high-performance register/primitive switching. */
# define R500_GA_ENHANCE_REG_READWRITE_NO_EFFECT (0 << 2) /* R520+ only */
# define R500_GA_ENHANCE_REG_READWRITE_ENABLE (1 << 2) /* R520+ only, Enables GA support of simultaneous register reads and writes. */
# define R500_GA_ENHANCE_REG_NOSTALL_NO_EFFECT (0 << 3)
# define R500_GA_ENHANCE_REG_NOSTALL_ENABLE (1 << 3) /* Enables GA support of no-stall reads for register read back. */
#define R600_GA_COLOR_CONTROL 0x4278
# define R600_GA_COLOR_CONTROL_RGB0_SHADING_SOLID (0 << 0)
@@ -1071,8 +891,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_GA_ROUND_MODE_RGB_CLAMP_FP20 (1 << 4)
# define R600_GA_ROUND_MODE_ALPHA_CLAMP_RGB (0 << 5)
# define R600_GA_ROUND_MODE_ALPHA_CLAMP_FP20 (1 << 5)
# define R500_GA_ROUND_MODE_GEOMETRY_MASK_SHIFT 6
# define R500_GA_ROUND_MODE_GEOMETRY_MASK_MASK 0x000003c0
/* Specifies x & y offsets for vertex data after conversion to FP.
* Offsets are in S15 format (subpixels -- 1/12 or 1/16, even in 8b
@@ -1195,40 +1013,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_RS_SEL_K0 4
# define R600_RS_SEL_K1 5
/* */
#define R500_RS_INST_0 0x4320
#define R500_RS_INST_1 0x4324
#define R500_RS_INST_2 0x4328
#define R500_RS_INST_3 0x432c
#define R500_RS_INST_4 0x4330
#define R500_RS_INST_5 0x4334
#define R500_RS_INST_6 0x4338
#define R500_RS_INST_7 0x433c
#define R500_RS_INST_8 0x4340
#define R500_RS_INST_9 0x4344
#define R500_RS_INST_10 0x4348
#define R500_RS_INST_11 0x434c
#define R500_RS_INST_12 0x4350
#define R500_RS_INST_13 0x4354
#define R500_RS_INST_14 0x4358
#define R500_RS_INST_15 0x435c
#define R500_RS_INST_TEX_ID_SHIFT 0
#define R500_RS_INST_TEX_CN_WRITE (1 << 4)
#define R500_RS_INST_TEX_ADDR_SHIFT 5
#define R500_RS_INST_COL_ID_SHIFT 12
#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16)
#define R500_RS_INST_COL_CN_WRITE (1 << 16)
#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16)
#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16)
#define R500_RS_INST_COL_ADDR_SHIFT 18
#define R500_RS_INST_TEX_ADJ (1 << 25)
#define R500_RS_INST_W_CN (1 << 26)
#define R500_RS_INST_TEX_ID(x) ((x) << R500_RS_INST_TEX_ID_SHIFT)
#define R500_RS_INST_TEX_ADDR(x) ((x) << R500_RS_INST_TEX_ADDR_SHIFT)
#define R500_RS_INST_COL_ID(x) ((x) << R500_RS_INST_COL_ID_SHIFT)
#define R500_RS_INST_COL_ADDR(x) ((x) << R500_RS_INST_COL_ADDR_SHIFT)
/* These DWORDs control how vertex data is routed into fragment program
* registers, after interpolators.
*/
@@ -1412,9 +1196,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_TX_TRI_PERF_3_8 (3<<15)
# define R600_ANISO_THRESHOLD_MASK (7<<17)
# define R500_MACRO_SWITCH (1<<22)
# define R500_BORDER_FIX (1<<31)
#define R600_TX_SIZE_0 0x4480
# define R600_TX_WIDTHMASK_SHIFT 0
# define R600_TX_WIDTHMASK_MASK (2047 << 0)
@@ -1432,9 +1213,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
They are given meanings as R, G, B and Alpha by the swizzle
specification */
# define R600_TX_FORMAT_X8 0x0
# define R500_TX_FORMAT_X1 0x0 // bit set in format 2
# define R600_TX_FORMAT_X16 0x1
# define R500_TX_FORMAT_X1_REV 0x0 // bit set in format 2
# define R600_TX_FORMAT_Y4X4 0x2
# define R600_TX_FORMAT_Y8X8 0x3
# define R600_TX_FORMAT_Y16X16 0x4
@@ -1521,14 +1300,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#define R600_TX_FORMAT2_0 0x4500 /* obvious missing in gap */
# define R600_TX_PITCHMASK_SHIFT 0
# define R600_TX_PITCHMASK_MASK (2047 << 0)
# define R500_TXFORMAT_MSB (1 << 14)
# define R500_TXWIDTH_BIT11 (1 << 15)
# define R500_TXHEIGHT_BIT11 (1 << 16)
# define R500_POW2FIX2FLT (1 << 17)
# define R500_SEL_FILTER4_TC0 (0 << 18)
# define R500_SEL_FILTER4_TC1 (1 << 18)
# define R500_SEL_FILTER4_TC2 (2 << 18)
# define R500_SEL_FILTER4_TC3 (3 << 18)
#define R600_TX_OFFSET_0 0x4540
#define R600_TX_OFFSET_1 0x4544
@@ -1983,9 +1754,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_FG_ALPHA_FUNC_DISABLE (0 << 11)
# define R600_FG_ALPHA_FUNC_ENABLE (1 << 11)
# define R500_FG_ALPHA_FUNC_10BIT (0 << 12)
# define R500_FG_ALPHA_FUNC_8BIT (1 << 12)
# define R600_FG_ALPHA_FUNC_MASK_DISABLE (0 << 16)
# define R600_FG_ALPHA_FUNC_MASK_ENABLE (1 << 16)
# define R600_FG_ALPHA_FUNC_CFG_2_OF_4 (0 << 17)
@@ -1994,24 +1762,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_FG_ALPHA_FUNC_DITH_DISABLE (0 << 20)
# define R600_FG_ALPHA_FUNC_DITH_ENABLE (1 << 20)
# define R500_FG_ALPHA_FUNC_OFFSET_DISABLE (0 << 24)
# define R500_FG_ALPHA_FUNC_OFFSET_ENABLE (1 << 24) /* Not supported in R520 */
# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_DISABLE (0 << 25)
# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_ENABLE (1 << 25)
# define R500_FG_ALPHA_FUNC_FP16_DISABLE (0 << 28)
# define R500_FG_ALPHA_FUNC_FP16_ENABLE (1 << 28)
/* Fog: Where does the depth come from? */
#define R600_FG_DEPTH_SRC 0x4bd8
# define R600_FG_DEPTH_SRC_SCAN (0 << 0)
# define R600_FG_DEPTH_SRC_SHADER (1 << 0)
/* Fog: Alpha Compare Value */
#define R500_FG_ALPHA_VALUE 0x4be0
# define R500_FG_ALPHA_VALUE_MASK 0x0000ffff
/* gap */
/* Fragment program parameters in 7.16 floating point */
@@ -2169,12 +1924,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_COLOR_ENDIAN_WORD_SWAP (1 << 19)
# define R600_COLOR_ENDIAN_DWORD_SWAP (2 << 19)
# define R600_COLOR_ENDIAN_HALF_DWORD_SWAP (3 << 19)
# define R500_COLOR_FORMAT_ARGB10101010 (0 << 21)
# define R500_COLOR_FORMAT_UV1010 (1 << 21)
# define R500_COLOR_FORMAT_CI8 (2 << 21) /* 2D only */
# define R600_COLOR_FORMAT_ARGB1555 (3 << 21)
# define R600_COLOR_FORMAT_RGB565 (4 << 21)
# define R500_COLOR_FORMAT_ARGB2101010 (5 << 21)
# define R600_COLOR_FORMAT_ARGB8888 (6 << 21)
# define R600_COLOR_FORMAT_ARGB32323232 (7 << 21)
/* reserved */
@@ -2183,7 +1934,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_COLOR_FORMAT_VYUY (11 << 21)
# define R600_COLOR_FORMAT_YVYU (12 << 21)
# define R600_COLOR_FORMAT_UV88 (13 << 21)
# define R500_COLOR_FORMAT_I10 (14 << 21)
# define R600_COLOR_FORMAT_ARGB4444 (15 << 21)
#define R600_RB3D_COLORPITCH1 0x4E3C
#define R600_RB3D_COLORPITCH2 0x4E40
@@ -2246,20 +1996,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_SAMPLE0 (0 << 2)
# define R600_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE (1 << 2)
/* Discard src pixels less than or equal to threshold. */
#define R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 0x4ea0
/* Discard src pixels greater than or equal to threshold. */
#define R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 0x4ea4
# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_SHIFT 0
# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_MASK 0x000000ff
# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_SHIFT 8
# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_MASK 0x0000ff00
# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_SHIFT 16
# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_MASK 0x00ff0000
# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_SHIFT 24
# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_MASK 0xff000000
/* 3D ROP Control. Stalls the 2d/3d datapath until it is idle. */
#define R600_RB3D_ROPCNTL 0x4e18
# define R600_RB3D_ROPCNTL_ROP_ENABLE 0x00000004
@@ -2269,27 +2005,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Color Compare Flip. Stalls the 2d/3d datapath until it is idle. */
#define R600_RB3D_CLRCMP_FLIPE 0x4e1c
/* Sets the fifo sizes */
#define R500_RB3D_FIFO_SIZE 0x4ef4
# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_FULL (0 << 0)
# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_HALF (1 << 0)
# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_QUATER (2 << 0)
# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_EIGTHS (3 << 0)
/* Constant color used by the blender. Pipelined through the blender. */
#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8
# define R500_RB3D_CONSTANT_COLOR_AR_RED_MASK 0x0000ffff
# define R500_RB3D_CONSTANT_COLOR_AR_RED_SHIFT 0
# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_MASK 0xffff0000
# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_SHIFT 16
/* Constant color used by the blender. Pipelined through the blender. */
#define R500_RB3D_CONSTANT_COLOR_GB 0x4efc
# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_MASK 0x0000ffff
# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_SHIFT 0
# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_MASK 0xffff0000
# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_SHIFT 16
/* gap */
/* There seems to be no "write only" setting, so use Z-test = ALWAYS
* for this.
@@ -2382,33 +2097,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
# define R600_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
# define R500_BMASK_ENABLE (0 << 10)
# define R500_BMASK_DISABLE (1 << 10)
# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
# define R500_PEQ_PACKING_DISABLE (0 << 18)
# define R500_PEQ_PACKING_ENABLE (1 << 18)
# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
/* gap */
/* Z Buffer Address Offset.
@@ -2460,23 +2148,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R600_DEPTHY_OFFSET_SHIFT 17
# define R600_DEPTHY_OFFSET_MASK 0x07FE0000
/* Sets the fifo sizes */
#define R500_ZB_FIFO_SIZE 0x4fd0
# define R500_OP_FIFO_SIZE_FULL (0 << 0)
# define R500_OP_FIFO_SIZE_HALF (1 << 0)
# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
/* Stencil Reference Value and Mask for backfacing quads */
/* R600_ZB_STENCILREFMASK handles front face */
#define R500_ZB_STENCILREFMASK_BF 0x4fd4
# define R500_STENCILREF_SHIFT 0
# define R500_STENCILREF_MASK 0x000000ff
# define R500_STENCILMASK_SHIFT 8
# define R500_STENCILMASK_MASK 0x0000ff00
# define R500_STENCILWRITEMASK_SHIFT 16
# define R500_STENCILWRITEMASK_MASK 0x00ff0000
/**
* \defgroup R3XX_R5XX_PROGRAMMABLE_VERTEX_SHADER_DESCRIPTION R3XX-R5XX PROGRAMMABLE VERTEX SHADER DESCRIPTION
*
@@ -2692,478 +2363,6 @@ enum {
#define R600_PRIM_NUM_VERTICES_SHIFT 16
#define R600_PRIM_NUM_VERTICES_MASK 0xffff
/*
* The R500 unified shader (US) registers come in banks of 512 each, one
* for each instruction slot in the shader. You can't touch them directly.
* R500_US_VECTOR_INDEX() sets the base instruction to modify; successive
* writes to R500_GA_US_VECTOR_DATA autoincrement the index after the
* instruction is fully specified.
*/
#define R500_US_ALU_ALPHA_INST_0 0xa800
# define R500_ALPHA_OP_MAD 0
# define R500_ALPHA_OP_DP 1
# define R500_ALPHA_OP_MIN 2
# define R500_ALPHA_OP_MAX 3
/* #define R500_ALPHA_OP_RESERVED 4 */
# define R500_ALPHA_OP_CND 5
# define R500_ALPHA_OP_CMP 6
# define R500_ALPHA_OP_FRC 7
# define R500_ALPHA_OP_EX2 8
# define R500_ALPHA_OP_LN2 9
# define R500_ALPHA_OP_RCP 10
# define R500_ALPHA_OP_RSQ 11
# define R500_ALPHA_OP_SIN 12
# define R500_ALPHA_OP_COS 13
# define R500_ALPHA_OP_MDH 14
# define R500_ALPHA_OP_MDV 15
# define R500_ALPHA_ADDRD(x) ((x) << 4)
# define R500_ALPHA_ADDRD_REL (1 << 11)
# define R500_ALPHA_SEL_A_SHIFT 12
# define R500_ALPHA_SEL_A_SRC0 (0 << 12)
# define R500_ALPHA_SEL_A_SRC1 (1 << 12)
# define R500_ALPHA_SEL_A_SRC2 (2 << 12)
# define R500_ALPHA_SEL_A_SRCP (3 << 12)
# define R500_ALPHA_SWIZ_A_R (0 << 14)
# define R500_ALPHA_SWIZ_A_G (1 << 14)
# define R500_ALPHA_SWIZ_A_B (2 << 14)
# define R500_ALPHA_SWIZ_A_A (3 << 14)
# define R500_ALPHA_SWIZ_A_0 (4 << 14)
# define R500_ALPHA_SWIZ_A_HALF (5 << 14)
# define R500_ALPHA_SWIZ_A_1 (6 << 14)
/* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */
# define R500_ALPHA_MOD_A_NOP (0 << 17)
# define R500_ALPHA_MOD_A_NEG (1 << 17)
# define R500_ALPHA_MOD_A_ABS (2 << 17)
# define R500_ALPHA_MOD_A_NAB (3 << 17)
# define R500_ALPHA_SEL_B_SHIFT 19
# define R500_ALPHA_SEL_B_SRC0 (0 << 19)
# define R500_ALPHA_SEL_B_SRC1 (1 << 19)
# define R500_ALPHA_SEL_B_SRC2 (2 << 19)
# define R500_ALPHA_SEL_B_SRCP (3 << 19)
# define R500_ALPHA_SWIZ_B_R (0 << 21)
# define R500_ALPHA_SWIZ_B_G (1 << 21)
# define R500_ALPHA_SWIZ_B_B (2 << 21)
# define R500_ALPHA_SWIZ_B_A (3 << 21)
# define R500_ALPHA_SWIZ_B_0 (4 << 21)
# define R500_ALPHA_SWIZ_B_HALF (5 << 21)
# define R500_ALPHA_SWIZ_B_1 (6 << 21)
/* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */
# define R500_ALPHA_MOD_B_NOP (0 << 24)
# define R500_ALPHA_MOD_B_NEG (1 << 24)
# define R500_ALPHA_MOD_B_ABS (2 << 24)
# define R500_ALPHA_MOD_B_NAB (3 << 24)
# define R500_ALPHA_OMOD_IDENTITY (0 << 26)
# define R500_ALPHA_OMOD_MUL_2 (1 << 26)
# define R500_ALPHA_OMOD_MUL_4 (2 << 26)
# define R500_ALPHA_OMOD_MUL_8 (3 << 26)
# define R500_ALPHA_OMOD_DIV_2 (4 << 26)
# define R500_ALPHA_OMOD_DIV_4 (5 << 26)
# define R500_ALPHA_OMOD_DIV_8 (6 << 26)
# define R500_ALPHA_OMOD_DISABLE (7 << 26)
# define R500_ALPHA_TARGET(x) ((x) << 29)
# define R500_ALPHA_W_OMASK (1 << 31)
#define R500_US_ALU_ALPHA_ADDR_0 0x9800
# define R500_ALPHA_ADDR0(x) ((x) << 0)
# define R500_ALPHA_ADDR0_CONST (1 << 8)
# define R500_ALPHA_ADDR0_REL (1 << 9)
# define R500_ALPHA_ADDR1(x) ((x) << 10)
# define R500_ALPHA_ADDR1_CONST (1 << 18)
# define R500_ALPHA_ADDR1_REL (1 << 19)
# define R500_ALPHA_ADDR2(x) ((x) << 20)
# define R500_ALPHA_ADDR2_CONST (1 << 28)
# define R500_ALPHA_ADDR2_REL (1 << 29)
# define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30)
# define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30)
# define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30)
# define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30)
#define R500_US_ALU_RGBA_INST_0 0xb000
# define R500_ALU_RGBA_OP_MAD (0 << 0)
# define R500_ALU_RGBA_OP_DP3 (1 << 0)
# define R500_ALU_RGBA_OP_DP4 (2 << 0)
# define R500_ALU_RGBA_OP_D2A (3 << 0)
# define R500_ALU_RGBA_OP_MIN (4 << 0)
# define R500_ALU_RGBA_OP_MAX (5 << 0)
/* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */
# define R500_ALU_RGBA_OP_CND (7 << 0)
# define R500_ALU_RGBA_OP_CMP (8 << 0)
# define R500_ALU_RGBA_OP_FRC (9 << 0)
# define R500_ALU_RGBA_OP_SOP (10 << 0)
# define R500_ALU_RGBA_OP_MDH (11 << 0)
# define R500_ALU_RGBA_OP_MDV (12 << 0)
# define R500_ALU_RGBA_ADDRD(x) ((x) << 4)
# define R500_ALU_RGBA_ADDRD_REL (1 << 11)
# define R500_ALU_RGBA_SEL_C_SHIFT 12
# define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12)
# define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12)
# define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12)
# define R500_ALU_RGBA_SEL_C_SRCP (3 << 12)
# define R500_ALU_RGBA_R_SWIZ_R (0 << 14)
# define R500_ALU_RGBA_R_SWIZ_G (1 << 14)
# define R500_ALU_RGBA_R_SWIZ_B (2 << 14)
# define R500_ALU_RGBA_R_SWIZ_A (3 << 14)
# define R500_ALU_RGBA_R_SWIZ_0 (4 << 14)
# define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14)
# define R500_ALU_RGBA_R_SWIZ_1 (6 << 14)
/* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */
# define R500_ALU_RGBA_G_SWIZ_R (0 << 17)
# define R500_ALU_RGBA_G_SWIZ_G (1 << 17)
# define R500_ALU_RGBA_G_SWIZ_B (2 << 17)
# define R500_ALU_RGBA_G_SWIZ_A (3 << 17)
# define R500_ALU_RGBA_G_SWIZ_0 (4 << 17)
# define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17)
# define R500_ALU_RGBA_G_SWIZ_1 (6 << 17)
/* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */
# define R500_ALU_RGBA_B_SWIZ_R (0 << 20)
# define R500_ALU_RGBA_B_SWIZ_G (1 << 20)
# define R500_ALU_RGBA_B_SWIZ_B (2 << 20)
# define R500_ALU_RGBA_B_SWIZ_A (3 << 20)
# define R500_ALU_RGBA_B_SWIZ_0 (4 << 20)
# define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20)
# define R500_ALU_RGBA_B_SWIZ_1 (6 << 20)
/* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */
# define R500_ALU_RGBA_MOD_C_NOP (0 << 23)
# define R500_ALU_RGBA_MOD_C_NEG (1 << 23)
# define R500_ALU_RGBA_MOD_C_ABS (2 << 23)
# define R500_ALU_RGBA_MOD_C_NAB (3 << 23)
# define R500_ALU_RGBA_ALPHA_SEL_C_SHIFT 25
# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25)
# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25)
# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25)
# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25)
# define R500_ALU_RGBA_A_SWIZ_R (0 << 27)
# define R500_ALU_RGBA_A_SWIZ_G (1 << 27)
# define R500_ALU_RGBA_A_SWIZ_B (2 << 27)
# define R500_ALU_RGBA_A_SWIZ_A (3 << 27)
# define R500_ALU_RGBA_A_SWIZ_0 (4 << 27)
# define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27)
# define R500_ALU_RGBA_A_SWIZ_1 (6 << 27)
/* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */
# define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30)
# define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30)
# define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30)
# define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30)
#define R500_US_ALU_RGB_INST_0 0xa000
# define R500_ALU_RGB_SEL_A_SHIFT 0
# define R500_ALU_RGB_SEL_A_SRC0 (0 << 0)
# define R500_ALU_RGB_SEL_A_SRC1 (1 << 0)
# define R500_ALU_RGB_SEL_A_SRC2 (2 << 0)
# define R500_ALU_RGB_SEL_A_SRCP (3 << 0)
# define R500_ALU_RGB_R_SWIZ_A_R (0 << 2)
# define R500_ALU_RGB_R_SWIZ_A_G (1 << 2)
# define R500_ALU_RGB_R_SWIZ_A_B (2 << 2)
# define R500_ALU_RGB_R_SWIZ_A_A (3 << 2)
# define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2)
# define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2)
# define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2)
/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */
# define R500_ALU_RGB_G_SWIZ_A_R (0 << 5)
# define R500_ALU_RGB_G_SWIZ_A_G (1 << 5)
# define R500_ALU_RGB_G_SWIZ_A_B (2 << 5)
# define R500_ALU_RGB_G_SWIZ_A_A (3 << 5)
# define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5)
# define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5)
# define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5)
/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */
# define R500_ALU_RGB_B_SWIZ_A_R (0 << 8)
# define R500_ALU_RGB_B_SWIZ_A_G (1 << 8)
# define R500_ALU_RGB_B_SWIZ_A_B (2 << 8)
# define R500_ALU_RGB_B_SWIZ_A_A (3 << 8)
# define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8)
# define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8)
# define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8)
/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */
# define R500_ALU_RGB_MOD_A_NOP (0 << 11)
# define R500_ALU_RGB_MOD_A_NEG (1 << 11)
# define R500_ALU_RGB_MOD_A_ABS (2 << 11)
# define R500_ALU_RGB_MOD_A_NAB (3 << 11)
# define R500_ALU_RGB_SEL_B_SHIFT 13
# define R500_ALU_RGB_SEL_B_SRC0 (0 << 13)
# define R500_ALU_RGB_SEL_B_SRC1 (1 << 13)
# define R500_ALU_RGB_SEL_B_SRC2 (2 << 13)
# define R500_ALU_RGB_SEL_B_SRCP (3 << 13)
# define R500_ALU_RGB_R_SWIZ_B_R (0 << 15)
# define R500_ALU_RGB_R_SWIZ_B_G (1 << 15)
# define R500_ALU_RGB_R_SWIZ_B_B (2 << 15)
# define R500_ALU_RGB_R_SWIZ_B_A (3 << 15)
# define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15)
# define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15)
# define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15)
/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */
# define R500_ALU_RGB_G_SWIZ_B_R (0 << 18)
# define R500_ALU_RGB_G_SWIZ_B_G (1 << 18)
# define R500_ALU_RGB_G_SWIZ_B_B (2 << 18)
# define R500_ALU_RGB_G_SWIZ_B_A (3 << 18)
# define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18)
# define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18)
# define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18)
/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */
# define R500_ALU_RGB_B_SWIZ_B_R (0 << 21)
# define R500_ALU_RGB_B_SWIZ_B_G (1 << 21)
# define R500_ALU_RGB_B_SWIZ_B_B (2 << 21)
# define R500_ALU_RGB_B_SWIZ_B_A (3 << 21)
# define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21)
# define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21)
# define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21)
/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */
# define R500_ALU_RGB_MOD_B_NOP (0 << 24)
# define R500_ALU_RGB_MOD_B_NEG (1 << 24)
# define R500_ALU_RGB_MOD_B_ABS (2 << 24)
# define R500_ALU_RGB_MOD_B_NAB (3 << 24)
# define R500_ALU_RGB_OMOD_IDENTITY (0 << 26)
# define R500_ALU_RGB_OMOD_MUL_2 (1 << 26)
# define R500_ALU_RGB_OMOD_MUL_4 (2 << 26)
# define R500_ALU_RGB_OMOD_MUL_8 (3 << 26)
# define R500_ALU_RGB_OMOD_DIV_2 (4 << 26)
# define R500_ALU_RGB_OMOD_DIV_4 (5 << 26)
# define R500_ALU_RGB_OMOD_DIV_8 (6 << 26)
# define R500_ALU_RGB_OMOD_DISABLE (7 << 26)
# define R500_ALU_RGB_TARGET(x) ((x) << 29)
# define R500_ALU_RGB_WMASK (1 << 31)
#define R500_US_ALU_RGB_ADDR_0 0x9000
# define R500_RGB_ADDR0(x) ((x) << 0)
# define R500_RGB_ADDR0_CONST (1 << 8)
# define R500_RGB_ADDR0_REL (1 << 9)
# define R500_RGB_ADDR1(x) ((x) << 10)
# define R500_RGB_ADDR1_CONST (1 << 18)
# define R500_RGB_ADDR1_REL (1 << 19)
# define R500_RGB_ADDR2(x) ((x) << 20)
# define R500_RGB_ADDR2_CONST (1 << 28)
# define R500_RGB_ADDR2_REL (1 << 29)
# define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30)
# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30)
# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30)
# define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30)
#define R500_US_CMN_INST_0 0xb800
# define R500_INST_TYPE_MASK (3 << 0)
# define R500_INST_TYPE_ALU (0 << 0)
# define R500_INST_TYPE_OUT (1 << 0)
# define R500_INST_TYPE_FC (2 << 0)
# define R500_INST_TYPE_TEX (3 << 0)
# define R500_INST_TEX_SEM_WAIT (1 << 2)
# define R500_INST_RGB_PRED_SEL_NONE (0 << 3)
# define R500_INST_RGB_PRED_SEL_RGBA (1 << 3)
# define R500_INST_RGB_PRED_SEL_RRRR (2 << 3)
# define R500_INST_RGB_PRED_SEL_GGGG (3 << 3)
# define R500_INST_RGB_PRED_SEL_BBBB (4 << 3)
# define R500_INST_RGB_PRED_SEL_AAAA (5 << 3)
# define R500_INST_RGB_PRED_INV (1 << 6)
# define R500_INST_WRITE_INACTIVE (1 << 7)
# define R500_INST_LAST (1 << 8)
# define R500_INST_NOP (1 << 9)
# define R500_INST_ALU_WAIT (1 << 10)
# define R500_INST_RGB_WMASK_R (1 << 11)
# define R500_INST_RGB_WMASK_G (1 << 12)
# define R500_INST_RGB_WMASK_B (1 << 13)
# define R500_INST_ALPHA_WMASK (1 << 14)
# define R500_INST_RGB_OMASK_R (1 << 15)
# define R500_INST_RGB_OMASK_G (1 << 16)
# define R500_INST_RGB_OMASK_B (1 << 17)
# define R500_INST_ALPHA_OMASK (1 << 18)
# define R500_INST_RGB_CLAMP (1 << 19)
# define R500_INST_ALPHA_CLAMP (1 << 20)
# define R500_INST_ALU_RESULT_SEL (1 << 21)
# define R500_INST_ALPHA_PRED_INV (1 << 22)
# define R500_INST_ALU_RESULT_OP_EQ (0 << 23)
# define R500_INST_ALU_RESULT_OP_LT (1 << 23)
# define R500_INST_ALU_RESULT_OP_GE (2 << 23)
# define R500_INST_ALU_RESULT_OP_NE (3 << 23)
# define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25)
# define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25)
# define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25)
# define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25)
# define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25)
# define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25)
/* XXX next four are kind of guessed */
# define R500_INST_STAT_WE_R (1 << 28)
# define R500_INST_STAT_WE_G (1 << 29)
# define R500_INST_STAT_WE_B (1 << 30)
# define R500_INST_STAT_WE_A (1 << 31)
/* note that these are 8 bit lengths, despite the offsets, at least for R500 */
#define R500_US_CODE_ADDR 0x4630
# define R500_US_CODE_START_ADDR(x) ((x) << 0)
# define R500_US_CODE_END_ADDR(x) ((x) << 16)
#define R500_US_CODE_OFFSET 0x4638
# define R500_US_CODE_OFFSET_ADDR(x) ((x) << 0)
#define R500_US_CODE_RANGE 0x4634
# define R500_US_CODE_RANGE_ADDR(x) ((x) << 0)
# define R500_US_CODE_RANGE_SIZE(x) ((x) << 16)
#define R500_US_CONFIG 0x4600
# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
#define R500_US_FC_ADDR_0 0xa000
# define R500_FC_BOOL_ADDR(x) ((x) << 0)
# define R500_FC_INT_ADDR(x) ((x) << 8)
# define R500_FC_JUMP_ADDR(x) ((x) << 16)
# define R500_FC_JUMP_GLOBAL (1 << 31)
#define R500_US_FC_BOOL_CONST 0x4620
# define R500_FC_KBOOL(x) (x)
#define R500_US_FC_CTRL 0x4624
# define R500_FC_TEST_EN (1 << 30)
# define R500_FC_FULL_FC_EN (1 << 31)
#define R500_US_FC_INST_0 0x9800
# define R500_FC_OP_JUMP (0 << 0)
# define R500_FC_OP_LOOP (1 << 0)
# define R500_FC_OP_ENDLOOP (2 << 0)
# define R500_FC_OP_REP (3 << 0)
# define R500_FC_OP_ENDREP (4 << 0)
# define R500_FC_OP_BREAKLOOP (5 << 0)
# define R500_FC_OP_BREAKREP (6 << 0)
# define R500_FC_OP_CONTINUE (7 << 0)
# define R500_FC_B_ELSE (1 << 4)
# define R500_FC_JUMP_ANY (1 << 5)
# define R500_FC_A_OP_NONE (0 << 6)
# define R500_FC_A_OP_POP (1 << 6)
# define R500_FC_A_OP_PUSH (2 << 6)
# define R500_FC_JUMP_FUNC(x) ((x) << 8)
# define R500_FC_B_POP_CNT(x) ((x) << 16)
# define R500_FC_B_OP0_NONE (0 << 24)
# define R500_FC_B_OP0_DECR (1 << 24)
# define R500_FC_B_OP0_INCR (2 << 24)
# define R500_FC_B_OP1_DECR (0 << 26)
# define R500_FC_B_OP1_NONE (1 << 26)
# define R500_FC_B_OP1_INCR (2 << 26)
# define R500_FC_IGNORE_UNCOVERED (1 << 28)
#define R500_US_FC_INT_CONST_0 0x4c00
# define R500_FC_INT_CONST_KR(x) ((x) << 0)
# define R500_FC_INT_CONST_KG(x) ((x) << 8)
# define R500_FC_INT_CONST_KB(x) ((x) << 16)
/* _0 through _15 */
#define R500_US_FORMAT0_0 0x4640
# define R500_FORMAT_TXWIDTH(x) ((x) << 0)
# define R500_FORMAT_TXHEIGHT(x) ((x) << 11)
# define R500_FORMAT_TXDEPTH(x) ((x) << 22)
/* _0 through _3 */
#define R500_US_OUT_FMT_0 0x46a4
# define R500_OUT_FMT_C4_8 (0 << 0)
# define R500_OUT_FMT_C4_10 (1 << 0)
# define R500_OUT_FMT_C4_10_GAMMA (2 << 0)
# define R500_OUT_FMT_C_16 (3 << 0)
# define R500_OUT_FMT_C2_16 (4 << 0)
# define R500_OUT_FMT_C4_16 (5 << 0)
# define R500_OUT_FMT_C_16_MPEG (6 << 0)
# define R500_OUT_FMT_C2_16_MPEG (7 << 0)
# define R500_OUT_FMT_C2_4 (8 << 0)
# define R500_OUT_FMT_C_3_3_2 (9 << 0)
# define R500_OUT_FMT_C_6_5_6 (10 << 0)
# define R500_OUT_FMT_C_11_11_10 (11 << 0)
# define R500_OUT_FMT_C_10_11_11 (12 << 0)
# define R500_OUT_FMT_C_2_10_10_10 (13 << 0)
/* #define R500_OUT_FMT_RESERVED (14 << 0) */
# define R500_OUT_FMT_UNUSED (15 << 0)
# define R500_OUT_FMT_C_16_FP (16 << 0)
# define R500_OUT_FMT_C2_16_FP (17 << 0)
# define R500_OUT_FMT_C4_16_FP (18 << 0)
# define R500_OUT_FMT_C_32_FP (19 << 0)
# define R500_OUT_FMT_C2_32_FP (20 << 0)
# define R500_OUT_FMT_C4_32_FP (21 << 0)
# define R500_C0_SEL_A (0 << 8)
# define R500_C0_SEL_R (1 << 8)
# define R500_C0_SEL_G (2 << 8)
# define R500_C0_SEL_B (3 << 8)
# define R500_C1_SEL_A (0 << 10)
# define R500_C1_SEL_R (1 << 10)
# define R500_C1_SEL_G (2 << 10)
# define R500_C1_SEL_B (3 << 10)
# define R500_C2_SEL_A (0 << 12)
# define R500_C2_SEL_R (1 << 12)
# define R500_C2_SEL_G (2 << 12)
# define R500_C2_SEL_B (3 << 12)
# define R500_C3_SEL_A (0 << 14)
# define R500_C3_SEL_R (1 << 14)
# define R500_C3_SEL_G (2 << 14)
# define R500_C3_SEL_B (3 << 14)
# define R500_OUT_SIGN(x) ((x) << 16)
# define R500_ROUND_ADJ (1 << 20)
#define R500_US_PIXSIZE 0x4604
# define R500_PIX_SIZE(x) (x)
#define R500_US_TEX_ADDR_0 0x9800
# define R500_TEX_SRC_ADDR(x) ((x) << 0)
# define R500_TEX_SRC_ADDR_REL (1 << 7)
# define R500_TEX_SRC_S_SWIZ_R (0 << 8)
# define R500_TEX_SRC_S_SWIZ_G (1 << 8)
# define R500_TEX_SRC_S_SWIZ_B (2 << 8)
# define R500_TEX_SRC_S_SWIZ_A (3 << 8)
# define R500_TEX_SRC_T_SWIZ_R (0 << 10)
# define R500_TEX_SRC_T_SWIZ_G (1 << 10)
# define R500_TEX_SRC_T_SWIZ_B (2 << 10)
# define R500_TEX_SRC_T_SWIZ_A (3 << 10)
# define R500_TEX_SRC_R_SWIZ_R (0 << 12)
# define R500_TEX_SRC_R_SWIZ_G (1 << 12)
# define R500_TEX_SRC_R_SWIZ_B (2 << 12)
# define R500_TEX_SRC_R_SWIZ_A (3 << 12)
# define R500_TEX_SRC_Q_SWIZ_R (0 << 14)
# define R500_TEX_SRC_Q_SWIZ_G (1 << 14)
# define R500_TEX_SRC_Q_SWIZ_B (2 << 14)
# define R500_TEX_SRC_Q_SWIZ_A (3 << 14)
# define R500_TEX_DST_ADDR(x) ((x) << 16)
# define R500_TEX_DST_ADDR_REL (1 << 23)
# define R500_TEX_DST_R_SWIZ_R (0 << 24)
# define R500_TEX_DST_R_SWIZ_G (1 << 24)
# define R500_TEX_DST_R_SWIZ_B (2 << 24)
# define R500_TEX_DST_R_SWIZ_A (3 << 24)
# define R500_TEX_DST_G_SWIZ_R (0 << 26)
# define R500_TEX_DST_G_SWIZ_G (1 << 26)
# define R500_TEX_DST_G_SWIZ_B (2 << 26)
# define R500_TEX_DST_G_SWIZ_A (3 << 26)
# define R500_TEX_DST_B_SWIZ_R (0 << 28)
# define R500_TEX_DST_B_SWIZ_G (1 << 28)
# define R500_TEX_DST_B_SWIZ_B (2 << 28)
# define R500_TEX_DST_B_SWIZ_A (3 << 28)
# define R500_TEX_DST_A_SWIZ_R (0 << 30)
# define R500_TEX_DST_A_SWIZ_G (1 << 30)
# define R500_TEX_DST_A_SWIZ_B (2 << 30)
# define R500_TEX_DST_A_SWIZ_A (3 << 30)
#define R500_US_TEX_ADDR_DXDY_0 0xa000
# define R500_DX_ADDR(x) ((x) << 0)
# define R500_DX_ADDR_REL (1 << 7)
# define R500_DX_S_SWIZ_R (0 << 8)
# define R500_DX_S_SWIZ_G (1 << 8)
# define R500_DX_S_SWIZ_B (2 << 8)
# define R500_DX_S_SWIZ_A (3 << 8)
# define R500_DX_T_SWIZ_R (0 << 10)
# define R500_DX_T_SWIZ_G (1 << 10)
# define R500_DX_T_SWIZ_B (2 << 10)
# define R500_DX_T_SWIZ_A (3 << 10)
# define R500_DX_R_SWIZ_R (0 << 12)
# define R500_DX_R_SWIZ_G (1 << 12)
# define R500_DX_R_SWIZ_B (2 << 12)
# define R500_DX_R_SWIZ_A (3 << 12)
# define R500_DX_Q_SWIZ_R (0 << 14)
# define R500_DX_Q_SWIZ_G (1 << 14)
# define R500_DX_Q_SWIZ_B (2 << 14)
# define R500_DX_Q_SWIZ_A (3 << 14)
# define R500_DY_ADDR(x) ((x) << 16)
# define R500_DY_ADDR_REL (1 << 17)
# define R500_DY_S_SWIZ_R (0 << 24)
# define R500_DY_S_SWIZ_G (1 << 24)
# define R500_DY_S_SWIZ_B (2 << 24)
# define R500_DY_S_SWIZ_A (3 << 24)
# define R500_DY_T_SWIZ_R (0 << 26)
# define R500_DY_T_SWIZ_G (1 << 26)
# define R500_DY_T_SWIZ_B (2 << 26)
# define R500_DY_T_SWIZ_A (3 << 26)
# define R500_DY_R_SWIZ_R (0 << 28)
# define R500_DY_R_SWIZ_G (1 << 28)
# define R500_DY_R_SWIZ_B (2 << 28)
# define R500_DY_R_SWIZ_A (3 << 28)
# define R500_DY_Q_SWIZ_R (0 << 30)
# define R500_DY_Q_SWIZ_G (1 << 30)
# define R500_DY_Q_SWIZ_B (2 << 30)
# define R500_DY_Q_SWIZ_A (3 << 30)
#define R500_US_TEX_INST_0 0x9000
# define R500_TEX_ID(x) ((x) << 16)
# define R500_TEX_INST_NOP (0 << 22)
# define R500_TEX_INST_LD (1 << 22)
# define R500_TEX_INST_TEXKILL (2 << 22)
# define R500_TEX_INST_PROJ (3 << 22)
# define R500_TEX_INST_LODBIAS (4 << 22)
# define R500_TEX_INST_LOD (5 << 22)
# define R500_TEX_INST_DXDY (6 << 22)
# define R500_TEX_SEM_ACQUIRE (1 << 25)
# define R500_TEX_IGNORE_UNCOVERED (1 << 26)
# define R500_TEX_UNSCALED (1 << 27)
#define R600_US_W_FMT 0x46b4
# define R600_W_FMT_W0 (0 << 0)
# define R600_W_FMT_W24 (1 << 0)
src/mesa/drivers/dri/r600/r600_render.c
+2 -11
View File
@@ -431,18 +431,9 @@ static int r600Fallback(GLcontext * ctx)
FALLBACK_IF(r600->radeon.Fallback);
/* Do we need to use new-style shaders?
* Also is there a better way to do this? */
if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
struct r500_fragment_program *fp = (struct r500_fragment_program *)
(char *)ctx->FragmentProgram._Current;
if (fp) {
if (!fp->translated) {
r500TranslateFragmentShader(r600, fp);
FALLBACK_IF(!fp->translated);
}
}
} else {
{
struct r600_fragment_program *fp = (struct r600_fragment_program *)
(char *)ctx->FragmentProgram._Current;
(char *)ctx->FragmentProgram._Current;
if (fp) {
if (!fp->translated) {
r600TranslateFragmentShader(r600, fp);
src/mesa/drivers/dri/r600/r600_shader.c
+7 -26
View File
@@ -12,7 +12,6 @@ static struct gl_program *r600NewProgram(GLcontext * ctx, GLenum target,
r600ContextPtr rmesa = R600_CONTEXT(ctx);
struct r600_vertex_program_cont *vp;
struct r600_fragment_program *r600_fp;
struct r500_fragment_program *r500_fp;
switch (target) {
case GL_VERTEX_STATE_PROGRAM_NV:
@@ -21,27 +20,13 @@ static struct gl_program *r600NewProgram(GLcontext * ctx, GLenum target,
return _mesa_init_vertex_program(ctx, &vp->mesa_program,
target, id);
case GL_FRAGMENT_PROGRAM_ARB:
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
r500_fp = CALLOC_STRUCT(r500_fragment_program);
r500_fp->ctx = ctx;
return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program,
target, id);
} else {
r600_fp = CALLOC_STRUCT(r600_fragment_program);
return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program,
target, id);
}
r600_fp = CALLOC_STRUCT(r600_fragment_program);
return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program,
target, id);
case GL_FRAGMENT_PROGRAM_NV:
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
r500_fp = CALLOC_STRUCT(r500_fragment_program);
return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program,
target, id);
} else {
r600_fp = CALLOC_STRUCT(r600_fragment_program);
return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program,
target, id);
}
r600_fp = CALLOC_STRUCT(r600_fragment_program);
return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program,
target, id);
default:
_mesa_problem(ctx, "Bad target in r600NewProgram");
}
@@ -60,17 +45,13 @@ r600ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog)
r600ContextPtr rmesa = R600_CONTEXT(ctx);
struct r600_vertex_program_cont *vp = (void *)prog;
struct r600_fragment_program *r600_fp = (struct r600_fragment_program *)prog;
struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)prog;
switch (target) {
case GL_VERTEX_PROGRAM_ARB:
vp->progs = NULL;
break;
case GL_FRAGMENT_PROGRAM_ARB:
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
r500_fp->translated = GL_FALSE;
else
r600_fp->translated = GL_FALSE;
r600_fp->translated = GL_FALSE;
break;
}
src/mesa/drivers/dri/r600/r600_state.c
+40 -392
View File
@@ -70,27 +70,17 @@ extern void _tnl_UpdateFixedFunctionProgram(GLcontext * ctx);
static void r600BlendColor(GLcontext * ctx, const GLfloat cf[4])
{
r600ContextPtr rmesa = R600_CONTEXT(ctx);
GLubyte color[4];
R600_STATECHANGE(rmesa, blend_color);
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
GLuint r = IROUND(cf[0]*1023.0f);
GLuint g = IROUND(cf[1]*1023.0f);
GLuint b = IROUND(cf[2]*1023.0f);
GLuint a = IROUND(cf[3]*1023.0f);
CLAMPED_FLOAT_TO_UBYTE(color[0], cf[0]);
CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]);
CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]);
CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]);
rmesa->hw.blend_color.cmd[1] = r | (a << 16);
rmesa->hw.blend_color.cmd[2] = b | (g << 16);
} else {
GLubyte color[4];
CLAMPED_FLOAT_TO_UBYTE(color[0], cf[0]);
CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]);
CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]);
CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]);
rmesa->hw.blend_color.cmd[1] = PACK_COLOR_8888(color[3], color[0],
color[1], color[2]);
}
rmesa->hw.blend_color.cmd[1] = PACK_COLOR_8888(color[3], color[0],
color[1], color[2]);
}
/**
@@ -364,10 +354,6 @@ static void r600ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
GLint p;
GLint *ip;
/* no VAP UCP on non-TCL chipsets */
if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
return;
p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
ip = (GLint *)ctx->Transform._ClipUserPlane[p];
@@ -383,10 +369,6 @@ static void r600SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
r600ContextPtr r600 = R600_CONTEXT(ctx);
GLuint p;
/* no VAP UCP on non-TCL chipsets */
if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
return;
p = cap - GL_CLIP_PLANE0;
R600_STATECHANGE(r600, vap_clip_cntl);
if (state) {
@@ -452,16 +434,10 @@ static GLboolean current_fragment_program_writes_depth(GLcontext* ctx)
{
r600ContextPtr r600 = R600_CONTEXT(ctx);
if (r600->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
struct r600_fragment_program *fp = (struct r600_fragment_program *)
(char *)ctx->FragmentProgram._Current;
return (fp && fp->WritesDepth);
} else {
struct r500_fragment_program* fp =
(struct r500_fragment_program*)(char*)
ctx->FragmentProgram._Current;
return (fp && fp->writes_depth);
}
struct r600_fragment_program *fp = (struct r600_fragment_program *)
(char *)ctx->FragmentProgram._Current;
return (fp && fp->WritesDepth);
}
static void r600SetEarlyZState(GLcontext * ctx)
@@ -523,7 +499,6 @@ static void r600SetAlphaState(GLcontext * ctx)
if (really_enabled) {
pp_misc |= R600_FG_ALPHA_FUNC_ENABLE;
pp_misc |= R500_FG_ALPHA_FUNC_8BIT;
pp_misc |= (refByte & R600_FG_ALPHA_FUNC_VAL_MASK);
} else {
pp_misc = 0x0;
@@ -1232,41 +1207,6 @@ static void r600SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings)
R600_US_TEX_INST_0, code->tex.length);
}
static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings)
{
int i;
struct r500_fragment_program *fp = (struct r500_fragment_program *)
(char *)ctx->FragmentProgram._Current;
struct r500_fragment_program_code *code = &fp->code;
/* find all the texture instructions and relocate the texture units */
for (i = 0; i < code->inst_end + 1; i++) {
if ((code->inst[i].inst0 & 0x3) == R500_INST_TYPE_TEX) {
uint32_t val;
int unit, opcode, new_unit;
val = code->inst[i].inst1;
unit = (val >> 16) & 0xf;
val &= ~(0xf << 16);
opcode = val & (0x7 << 22);
if (opcode == R500_TEX_INST_TEXKILL) {
new_unit = 0;
} else {
if (tmu_mappings[unit] >= 0) {
new_unit = tmu_mappings[unit];
} else {
new_unit = 0;
}
}
val |= R500_TEX_ID(new_unit);
code->inst[i].inst1 = val;
}
}
}
static GLuint translate_lod_bias(GLfloat bias)
{
GLint b = (int)(bias*32);
@@ -1391,18 +1331,15 @@ static void r600SetupTextures(GLcontext * ctx)
if (!fp) /* should only happenen once, just after context is created */
return;
if (r600->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
if (fp->mesa_program.UsesKill && last_hw_tmu < 0) {
// The KILL operation requires the first texture unit
// to be enabled.
r600->hw.txe.cmd[R600_TXE_ENABLE] |= 1;
r600->hw.tex.filter.cmd[R600_TEX_VALUE_0] = 0;
r600->hw.tex.filter.cmd[R600_TEX_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, 1);
}
r600SetupFragmentShaderTextures(ctx, tmu_mappings);
} else
r500SetupFragmentShaderTextures(ctx, tmu_mappings);
if (fp->mesa_program.UsesKill && last_hw_tmu < 0) {
// The KILL operation requires the first texture unit
// to be enabled.
r600->hw.txe.cmd[R600_TXE_ENABLE] |= 1;
r600->hw.tex.filter.cmd[R600_TEX_VALUE_0] = 0;
r600->hw.tex.filter.cmd[R600_TEX_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, 1);
}
r600SetupFragmentShaderTextures(ctx, tmu_mappings);
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "TX_ENABLE: %08x last_hw_tmu=%d\n",
@@ -1569,187 +1506,6 @@ static void r600SetupRSUnit(GLcontext * ctx)
WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
}
static void r500SetupRSUnit(GLcontext * ctx)
{
r600ContextPtr r600 = R600_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
union r600_outputs_written OutputsWritten;
GLuint InputsRead;
int fp_reg, high_rr;
int col_ip, tex_ip;
int rs_tex_count = 0;
int i, count, col_fmt;
if (hw_tcl_on)
OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
else
RENDERINPUTS_COPY(OutputsWritten.index_bitset, r600->state.render_inputs_bitset);
if (ctx->FragmentProgram._Current)
InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
else {
fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
return; /* This should only ever happen once.. */
}
R600_STATECHANGE(r600, ri);
R600_STATECHANGE(r600, rc);
R600_STATECHANGE(r600, rr);
fp_reg = col_ip = tex_ip = col_fmt = 0;
r600->hw.rc.cmd[1] = 0;
r600->hw.rc.cmd[2] = 0;
for (i=0; i<R600_RR_CMDSIZE-1; ++i)
r600->hw.rr.cmd[R600_RR_INST_0 + i] = 0;
for (i=0; i<R500_RI_CMDSIZE-1; ++i)
r600->hw.ri.cmd[R600_RI_INTERP_0 + i] = 0;
if (InputsRead & FRAG_BIT_COL0) {
if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size;
if (count == 4)
col_fmt = R600_RS_COL_FMT_RGBA;
else if (count == 3)
col_fmt = R600_RS_COL_FMT_RGB1;
else
col_fmt = R600_RS_COL_FMT_0001;
r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt);
r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_COL0;
++col_ip;
++fp_reg;
} else {
WARN_ONCE("fragprog wants col0, vp doesn't provide it\n");
}
}
if (InputsRead & FRAG_BIT_COL1) {
if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size;
if (count == 4)
col_fmt = R600_RS_COL_FMT_RGBA;
else if (count == 3)
col_fmt = R600_RS_COL_FMT_RGB1;
else
col_fmt = R600_RS_COL_FMT_0001;
r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt);
r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_COL1;
++col_ip;
++fp_reg;
} else {
WARN_ONCE("fragprog wants col1, vp doesn't provide it\n");
}
}
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
if (! ( InputsRead & FRAG_BIT_TEX(i) ) )
continue;
if (!R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
continue;
}
int swiz = 0;
/* with TCL we always seem to route 4 components */
if (hw_tcl_on)
count = 4;
else
count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size;
if (count == 4) {
swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT;
swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT;
swiz |= (rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT;
swiz |= (rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT;
} else if (count == 3) {
swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT;
swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT;
swiz |= (rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT;
swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT;
} else if (count == 2) {
swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT;
swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT;
swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT;
swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT;
} else if (count == 1) {
swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT;
swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT;
swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT;
swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT;
} else {
swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT;
swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT;
swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT;
swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT;
}
r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= swiz;
r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
InputsRead &= ~(FRAG_BIT_TEX0 << i);
rs_tex_count += count;
++tex_ip;
++fp_reg;
}
if (InputsRead & FRAG_BIT_FOGC) {
if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) {
r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) |
((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) |
((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) |
((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT);
r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_FOGC;
rs_tex_count += 4;
++tex_ip;
++fp_reg;
} else {
WARN_ONCE("fragprog wants fogc, vp doesn't provide it\n");
}
}
if (InputsRead & FRAG_BIT_WPOS) {
r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) |
((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) |
((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) |
((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT);
r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
InputsRead &= ~FRAG_BIT_WPOS;
rs_tex_count += 4;
++tex_ip;
++fp_reg;
}
/* Setup default color if no color or tex was set */
if (rs_tex_count == 0 && col_ip == 0) {
r600->hw.rr.cmd[R600_RR_INST_0] |= R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(0) | R500_RS_COL_FMT(R600_RS_COL_FMT_0001);
++col_ip;
}
high_rr = (col_ip > tex_ip) ? col_ip : tex_ip;
r600->hw.rc.cmd[1] |= (rs_tex_count << R600_IT_COUNT_SHIFT) | (col_ip << R600_IC_COUNT_SHIFT) | R600_HIRES_EN;
r600->hw.rc.cmd[2] |= 0xC0 | (high_rr - 1);
r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_INST_0, high_rr);
if (InputsRead)
WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
}
#define bump_vpu_count(ptr, new_count) do{\
drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
int _nc=(new_count)/4; \
@@ -1827,8 +1583,6 @@ static void r600VapCntl(r600ContextPtr rmesa, GLuint input_count,
(pvs_num_slots << R600_PVS_NUM_SLOTS_SHIFT) |
(pvs_num_cntrls << R600_PVS_NUM_CNTLRS_SHIFT) |
(12 << R600_VF_MAX_VTX_NUM_SHIFT);
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= R500_TCL_STATE_OPTIMIZATION;
} else
/* not sure about non-tcl */
rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] = ((10 << R600_PVS_NUM_SLOTS_SHIFT) |
@@ -2030,10 +1784,6 @@ static void r600Enable(GLcontext * ctx, GLenum cap, GLboolean state)
static void r600ResetHwState(r600ContextPtr r600)
{
GLcontext *ctx = r600->radeon.glCtx;
int has_tcl = 1;
if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
has_tcl = 0;
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "%s\n", __FUNCTION__);
@@ -2083,29 +1833,22 @@ static void r600ResetHwState(r600ContextPtr r600)
r600->hw.vap_cntl_status.cmd[1] = R600_VC_32BIT_SWAP;
#endif
/* disable VAP/TCL on non-TCL capable chips */
if (!has_tcl)
r600->hw.vap_cntl_status.cmd[1] |= R600_VAP_TCL_BYPASS;
r600->hw.vap_psc_sgn_norm_cntl.cmd[1] = 0xAAAAAAAA;
/* XXX: Other families? */
if (has_tcl) {
r600->hw.vap_clip_cntl.cmd[1] = R600_PS_UCP_MODE_DIST_COP;
r600->hw.vap_clip_cntl.cmd[1] = R600_PS_UCP_MODE_DIST_COP;
r600->hw.vap_clip.cmd[1] = r600PackFloat32(1.0); /* X */
r600->hw.vap_clip.cmd[2] = r600PackFloat32(1.0); /* X */
r600->hw.vap_clip.cmd[3] = r600PackFloat32(1.0); /* Y */
r600->hw.vap_clip.cmd[4] = r600PackFloat32(1.0); /* Y */
r600->hw.vap_clip.cmd[1] = r600PackFloat32(1.0); /* X */
r600->hw.vap_clip.cmd[2] = r600PackFloat32(1.0); /* X */
r600->hw.vap_clip.cmd[3] = r600PackFloat32(1.0); /* Y */
r600->hw.vap_clip.cmd[4] = r600PackFloat32(1.0); /* Y */
switch (r600->radeon.radeonScreen->chip_family) {
case CHIP_FAMILY_R600:
r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_R600;
break;
default:
r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_RV350;
break;
}
switch (r600->radeon.radeonScreen->chip_family) {
case CHIP_FAMILY_R600:
r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_R600;
break;
default:
r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_RV350;
break;
}
r600->hw.gb_enable.cmd[1] = R600_GB_POINT_STUFF_ENABLE
@@ -2180,14 +1923,6 @@ static void r600ResetHwState(r600ContextPtr r600)
r600->hw.sc_screendoor.cmd[1] = 0x00FFFFFF;
r600->hw.us_out_fmt.cmd[1] = R500_OUT_FMT_C4_8 |
R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
r600->hw.us_out_fmt.cmd[2] = R500_OUT_FMT_UNUSED |
R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
r600->hw.us_out_fmt.cmd[3] = R500_OUT_FMT_UNUSED |
R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
r600->hw.us_out_fmt.cmd[4] = R500_OUT_FMT_UNUSED |
R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
r600->hw.us_out_fmt.cmd[5] = R600_W_FMT_W0 | R600_W_SRC_US;
/* disable fog unit */
@@ -2210,9 +1945,6 @@ static void r600ResetHwState(r600ContextPtr r600)
r600->hw.rb3d_aaresolve_ctl.cmd[1] = 0;
r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000;
r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff;
r600->hw.zb_depthclearvalue.cmd[1] = 0;
r600->hw.zstencil_format.cmd[2] = R600_ZTOP_DISABLE;
@@ -2228,12 +1960,11 @@ static void r600ResetHwState(r600ContextPtr r600)
r600->hw.zb_hiz_pitch.cmd[1] = 0;
r600VapCntl(r600, 0, 0, 0);
if (has_tcl) {
r600->hw.vps.cmd[R600_VPS_ZERO_0] = 0;
r600->hw.vps.cmd[R600_VPS_ZERO_1] = 0;
r600->hw.vps.cmd[R600_VPS_POINTSIZE] = r600PackFloat32(1.0);
r600->hw.vps.cmd[R600_VPS_ZERO_3] = 0;
}
r600->hw.vps.cmd[R600_VPS_ZERO_0] = 0;
r600->hw.vps.cmd[R600_VPS_ZERO_1] = 0;
r600->hw.vps.cmd[R600_VPS_POINTSIZE] = r600PackFloat32(1.0);
r600->hw.vps.cmd[R600_VPS_ZERO_3] = 0;
r600->radeon.hw.all_dirty = GL_TRUE;
}
@@ -2371,82 +2102,6 @@ static void r600SetupPixelShader(r600ContextPtr rmesa)
}
}
#define bump_r500fp_count(ptr, new_count) do{\
drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
int _nc=(new_count)/6; \
assert(_nc < 256); \
if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
} while(0)
#define bump_r500fp_const_count(ptr, new_count) do{\
drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
int _nc=(new_count)/4; \
assert(_nc < 256); \
if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
} while(0)
static void r500SetupPixelShader(r600ContextPtr rmesa)
{
GLcontext *ctx = rmesa->radeon.glCtx;
struct r500_fragment_program *fp = (struct r500_fragment_program *)
(char *)ctx->FragmentProgram._Current;
int i;
struct r500_fragment_program_code *code;
if (!fp) /* should only happenen once, just after context is created */
return;
((drm_r300_cmd_header_t *) rmesa->hw.r500fp.cmd)->r500fp.count = 0;
((drm_r300_cmd_header_t *) rmesa->hw.r500fp_const.cmd)->r500fp.count = 0;
r500TranslateFragmentShader(rmesa, fp);
if (!fp->translated) {
fprintf(stderr, "%s: No valid fragment shader, exiting\n",
__FUNCTION__);
return;
}
code = &fp->code;
r600SetupTextures(ctx);
R600_STATECHANGE(rmesa, fp);
rmesa->hw.fp.cmd[R500_FP_PIXSIZE] = code->max_temp_idx;
rmesa->hw.fp.cmd[R500_FP_CODE_ADDR] =
R500_US_CODE_START_ADDR(code->inst_offset) |
R500_US_CODE_END_ADDR(code->inst_end);
rmesa->hw.fp.cmd[R500_FP_CODE_RANGE] =
R500_US_CODE_RANGE_ADDR(code->inst_offset) |
R500_US_CODE_RANGE_SIZE(code->inst_end);
rmesa->hw.fp.cmd[R500_FP_CODE_OFFSET] =
R500_US_CODE_OFFSET_ADDR(0); /* FIXME when we add flow control */
R600_STATECHANGE(rmesa, r500fp);
/* Emit our shader... */
for (i = 0; i < code->inst_end+1; i++) {
rmesa->hw.r500fp.cmd[i*6+1] = code->inst[i].inst0;
rmesa->hw.r500fp.cmd[i*6+2] = code->inst[i].inst1;
rmesa->hw.r500fp.cmd[i*6+3] = code->inst[i].inst2;
rmesa->hw.r500fp.cmd[i*6+4] = code->inst[i].inst3;
rmesa->hw.r500fp.cmd[i*6+5] = code->inst[i].inst4;
rmesa->hw.r500fp.cmd[i*6+6] = code->inst[i].inst5;
}
bump_r500fp_count(rmesa->hw.r500fp.cmd, (code->inst_end + 1) * 6);
R600_STATECHANGE(rmesa, r500fp_const);
for (i = 0; i < code->const_nr; i++) {
const GLfloat *constant = get_fragmentprogram_constant(ctx,
&fp->mesa_program.Base, code->constant[i]);
rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 0] = r600PackFloat32(constant[0]);
rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 1] = r600PackFloat32(constant[1]);
rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 2] = r600PackFloat32(constant[2]);
rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 3] = r600PackFloat32(constant[3]);
}
bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, code->const_nr * 4);
}
void r600UpdateShaderStates(r600ContextPtr rmesa)
{
GLcontext *ctx;
@@ -2475,18 +2130,11 @@ void r600UpdateShaderStates(r600ContextPtr rmesa)
rmesa->hw.fg_depth_src.cmd[1] = fgdepthsrc;
}
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
r500SetupPixelShader(rmesa);
else
r600SetupPixelShader(rmesa);
r600SetupPixelShader(rmesa);
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
r500SetupRSUnit(ctx);
else
r600SetupRSUnit(ctx);
r600SetupRSUnit(ctx);
if ((rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
r600SetupVertexProgram(rmesa);
r600SetupVertexProgram(rmesa);
}
src/mesa/drivers/dri/r600/r600_texstate.c
-12
View File
@@ -239,12 +239,6 @@ static void setup_hardware_state(r600ContextPtr rmesa, radeonTexObj *t)
t->pp_txpitch = ((firstImage->Width + align) & ~align) - 1;
}
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
if (firstImage->Width > 2048)
t->pp_txpitch |= R500_TXWIDTH_BIT11;
if (firstImage->Height > 2048)
t->pp_txpitch |= R500_TXHEIGHT_BIT11;
}
}
/**
@@ -471,12 +465,6 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
t->pp_txsize |= R600_TX_SIZE_TXPITCH_EN;
t->pp_txpitch |= pitch_val;
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
if (rb->width > 2048)
t->pp_txpitch |= R500_TXWIDTH_BIT11;
if (rb->height > 2048)
t->pp_txpitch |= R500_TXHEIGHT_BIT11;
}
t->validated = GL_TRUE;
_mesa_unlock_texture(radeon->glCtx, texObj);
return;
src/mesa/drivers/dri/r600/r700_fragprog.c
-719
View File
@@ -1,719 +0,0 @@
/*
* Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "r700_fragprog.h"
#include "radeon_nqssadce.h"
#include "radeon_program_alu.h"
static void reset_srcreg(struct prog_src_register* reg)
{
_mesa_bzero(reg, sizeof(*reg));
reg->Swizzle = SWIZZLE_NOOP;
}
static struct prog_src_register shadow_ambient(struct gl_program *program, int tmu)
{
gl_state_index fail_value_tokens[STATE_LENGTH] = {
STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0
};
struct prog_src_register reg = { 0, };
fail_value_tokens[2] = tmu;
reg.File = PROGRAM_STATE_VAR;
reg.Index = _mesa_add_state_reference(program->Parameters, fail_value_tokens);
reg.Swizzle = SWIZZLE_WWWW;
return reg;
}
/**
* Transform TEX, TXP, TXB, and KIL instructions in the following way:
* - premultiply texture coordinates for RECT
* - extract operand swizzles
* - introduce a temporary register when write masks are needed
*
*/
static GLboolean transform_TEX(
struct radeon_transform_context *t,
struct prog_instruction* orig_inst, void* data)
{
struct r500_fragment_program_compiler *compiler =
(struct r500_fragment_program_compiler*)data;
struct prog_instruction inst = *orig_inst;
struct prog_instruction* tgt;
GLboolean destredirect = GL_FALSE;
if (inst.Opcode != OPCODE_TEX &&
inst.Opcode != OPCODE_TXB &&
inst.Opcode != OPCODE_TXP &&
inst.Opcode != OPCODE_KIL)
return GL_FALSE;
/* ARB_shadow & EXT_shadow_funcs */
if (inst.Opcode != OPCODE_KIL &&
t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) {
GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func;
if (comparefunc == GL_NEVER || comparefunc == GL_ALWAYS) {
tgt = radeonAppendInstructions(t->Program, 1);
tgt->Opcode = OPCODE_MOV;
tgt->DstReg = inst.DstReg;
if (comparefunc == GL_ALWAYS) {
tgt->SrcReg[0].File = PROGRAM_BUILTIN;
tgt->SrcReg[0].Swizzle = SWIZZLE_1111;
} else {
tgt->SrcReg[0] = shadow_ambient(t->Program, inst.TexSrcUnit);
}
return GL_TRUE;
}
inst.DstReg.File = PROGRAM_TEMPORARY;
inst.DstReg.Index = radeonFindFreeTemporary(t);
inst.DstReg.WriteMask = WRITEMASK_XYZW;
} else if (inst.Opcode != OPCODE_KIL && inst.DstReg.File != PROGRAM_TEMPORARY) {
int tempreg = radeonFindFreeTemporary(t);
inst.DstReg.File = PROGRAM_TEMPORARY;
inst.DstReg.Index = tempreg;
inst.DstReg.WriteMask = WRITEMASK_XYZW;
destredirect = GL_TRUE;
}
if (inst.SrcReg[0].File != PROGRAM_TEMPORARY && inst.SrcReg[0].File != PROGRAM_INPUT) {
int tmpreg = radeonFindFreeTemporary(t);
tgt = radeonAppendInstructions(t->Program, 1);
tgt->Opcode = OPCODE_MOV;
tgt->DstReg.File = PROGRAM_TEMPORARY;
tgt->DstReg.Index = tmpreg;
tgt->SrcReg[0] = inst.SrcReg[0];
reset_srcreg(&inst.SrcReg[0]);
inst.SrcReg[0].File = PROGRAM_TEMPORARY;
inst.SrcReg[0].Index = tmpreg;
}
tgt = radeonAppendInstructions(t->Program, 1);
_mesa_copy_instructions(tgt, &inst, 1);
if (inst.Opcode != OPCODE_KIL &&
t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) {
GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func;
GLuint depthmode = compiler->fp->state.unit[inst.TexSrcUnit].depth_texture_mode;
int rcptemp = radeonFindFreeTemporary(t);
int pass, fail;
tgt = radeonAppendInstructions(t->Program, 3);
tgt[0].Opcode = OPCODE_RCP;
tgt[0].DstReg.File = PROGRAM_TEMPORARY;
tgt[0].DstReg.Index = rcptemp;
tgt[0].DstReg.WriteMask = WRITEMASK_W;
tgt[0].SrcReg[0] = inst.SrcReg[0];
tgt[0].SrcReg[0].Swizzle = SWIZZLE_WWWW;
tgt[1].Opcode = OPCODE_MAD;
tgt[1].DstReg = inst.DstReg;
tgt[1].DstReg.WriteMask = orig_inst->DstReg.WriteMask;
tgt[1].SrcReg[0] = inst.SrcReg[0];
tgt[1].SrcReg[0].Swizzle = SWIZZLE_ZZZZ;
tgt[1].SrcReg[1].File = PROGRAM_TEMPORARY;
tgt[1].SrcReg[1].Index = rcptemp;
tgt[1].SrcReg[1].Swizzle = SWIZZLE_WWWW;
tgt[1].SrcReg[2].File = PROGRAM_TEMPORARY;
tgt[1].SrcReg[2].Index = inst.DstReg.Index;
if (depthmode == 0) /* GL_LUMINANCE */
tgt[1].SrcReg[2].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z);
else if (depthmode == 2) /* GL_ALPHA */
tgt[1].SrcReg[2].Swizzle = SWIZZLE_WWWW;
/* Recall that SrcReg[0] is tex, SrcReg[2] is r and:
* r < tex <=> -tex+r < 0
* r >= tex <=> not (-tex+r < 0 */
if (comparefunc == GL_LESS || comparefunc == GL_GEQUAL)
tgt[1].SrcReg[2].NegateBase = tgt[0].SrcReg[2].NegateBase ^ NEGATE_XYZW;
else
tgt[1].SrcReg[0].NegateBase = tgt[0].SrcReg[0].NegateBase ^ NEGATE_XYZW;
tgt[2].Opcode = OPCODE_CMP;
tgt[2].DstReg = orig_inst->DstReg;
tgt[2].SrcReg[0].File = PROGRAM_TEMPORARY;
tgt[2].SrcReg[0].Index = tgt[1].DstReg.Index;
if (comparefunc == GL_LESS || comparefunc == GL_GREATER) {
pass = 1;
fail = 2;
} else {
pass = 2;
fail = 1;
}
tgt[2].SrcReg[pass].File = PROGRAM_BUILTIN;
tgt[2].SrcReg[pass].Swizzle = SWIZZLE_1111;
tgt[2].SrcReg[fail] = shadow_ambient(t->Program, inst.TexSrcUnit);
} else if (destredirect) {
tgt = radeonAppendInstructions(t->Program, 1);
tgt->Opcode = OPCODE_MOV;
tgt->DstReg = orig_inst->DstReg;
tgt->SrcReg[0].File = PROGRAM_TEMPORARY;
tgt->SrcReg[0].Index = inst.DstReg.Index;
}
return GL_TRUE;
}
static void update_params(r600ContextPtr r600, struct r500_fragment_program *fp)
{
struct gl_fragment_program *mp = &fp->mesa_program;
/* Ask Mesa nicely to fill in ParameterValues for us */
if (mp->Base.Parameters)
_mesa_load_state_parameters(r600->radeon.glCtx, mp->Base.Parameters);
}
/**
* Transform the program to support fragment.position.
*
* Introduce a small fragment at the start of the program that will be
* the only code that directly reads the FRAG_ATTRIB_WPOS input.
* All other code pieces that reference that input will be rewritten
* to read from a newly allocated temporary.
*
* \todo if/when r5xx supports the radeon_program architecture, this is a
* likely candidate for code sharing.
*/
static void insert_WPOS_trailer(struct r500_fragment_program_compiler *compiler)
{
GLuint InputsRead = compiler->fp->mesa_program.Base.InputsRead;
if (!(InputsRead & FRAG_BIT_WPOS))
return;
static gl_state_index tokens[STATE_LENGTH] = {
STATE_INTERNAL, STATE_R600_WINDOW_DIMENSION, 0, 0, 0
};
struct prog_instruction *fpi;
GLuint window_index;
int i = 0;
GLuint tempregi = _mesa_find_free_register(compiler->program, PROGRAM_TEMPORARY);
_mesa_insert_instructions(compiler->program, 0, 3);
fpi = compiler->program->Instructions;
/* perspective divide */
fpi[i].Opcode = OPCODE_RCP;
fpi[i].DstReg.File = PROGRAM_TEMPORARY;
fpi[i].DstReg.Index = tempregi;
fpi[i].DstReg.WriteMask = WRITEMASK_W;
fpi[i].DstReg.CondMask = COND_TR;
fpi[i].SrcReg[0].File = PROGRAM_INPUT;
fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS;
fpi[i].SrcReg[0].Swizzle = SWIZZLE_WWWW;
i++;
fpi[i].Opcode = OPCODE_MUL;
fpi[i].DstReg.File = PROGRAM_TEMPORARY;
fpi[i].DstReg.Index = tempregi;
fpi[i].DstReg.WriteMask = WRITEMASK_XYZ;
fpi[i].DstReg.CondMask = COND_TR;
fpi[i].SrcReg[0].File = PROGRAM_INPUT;
fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS;
fpi[i].SrcReg[0].Swizzle = SWIZZLE_XYZW;
fpi[i].SrcReg[1].File = PROGRAM_TEMPORARY;
fpi[i].SrcReg[1].Index = tempregi;
fpi[i].SrcReg[1].Swizzle = SWIZZLE_WWWW;
i++;
/* viewport transformation */
window_index = _mesa_add_state_reference(compiler->program->Parameters, tokens);
fpi[i].Opcode = OPCODE_MAD;
fpi[i].DstReg.File = PROGRAM_TEMPORARY;
fpi[i].DstReg.Index = tempregi;
fpi[i].DstReg.WriteMask = WRITEMASK_XYZ;
fpi[i].DstReg.CondMask = COND_TR;
fpi[i].SrcReg[0].File = PROGRAM_TEMPORARY;
fpi[i].SrcReg[0].Index = tempregi;
fpi[i].SrcReg[0].Swizzle =
MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO);
fpi[i].SrcReg[1].File = PROGRAM_STATE_VAR;
fpi[i].SrcReg[1].Index = window_index;
fpi[i].SrcReg[1].Swizzle =
MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO);
fpi[i].SrcReg[2].File = PROGRAM_STATE_VAR;
fpi[i].SrcReg[2].Index = window_index;
fpi[i].SrcReg[2].Swizzle =
MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO);
i++;
for (; i < compiler->program->NumInstructions; ++i) {
int reg;
for (reg = 0; reg < 3; reg++) {
if (fpi[i].SrcReg[reg].File == PROGRAM_INPUT &&
fpi[i].SrcReg[reg].Index == FRAG_ATTRIB_WPOS) {
fpi[i].SrcReg[reg].File = PROGRAM_TEMPORARY;
fpi[i].SrcReg[reg].Index = tempregi;
}
}
}
}
static void nqssadce_init(struct nqssadce_state* s)
{
s->Outputs[FRAG_RESULT_COLOR].Sourced = WRITEMASK_XYZW;
s->Outputs[FRAG_RESULT_DEPTH].Sourced = WRITEMASK_W;
}
static GLboolean is_native_swizzle(GLuint opcode, struct prog_src_register reg)
{
GLuint relevant;
int i;
if (opcode == OPCODE_TEX ||
opcode == OPCODE_TXB ||
opcode == OPCODE_TXP ||
opcode == OPCODE_KIL) {
if (reg.Abs)
return GL_FALSE;
if (reg.NegateAbs)
reg.NegateBase ^= 15;
if (opcode == OPCODE_KIL) {
if (reg.Swizzle != SWIZZLE_NOOP)
return GL_FALSE;
} else {
for(i = 0; i < 4; ++i) {
GLuint swz = GET_SWZ(reg.Swizzle, i);
if (swz == SWIZZLE_NIL) {
reg.NegateBase &= ~(1 << i);
continue;
}
if (swz >= 4)
return GL_FALSE;
}
}
if (reg.NegateBase)
return GL_FALSE;
return GL_TRUE;
} else if (opcode == OPCODE_DDX || opcode == OPCODE_DDY) {
/* DDX/MDH and DDY/MDV explicitly ignore incoming swizzles;
* if it doesn't fit perfectly into a .xyzw case... */
if (reg.Swizzle == SWIZZLE_NOOP && !reg.Abs
&& !reg.NegateBase && !reg.NegateAbs)
return GL_TRUE;
return GL_FALSE;
} else {
/* ALU instructions support almost everything */
if (reg.Abs)
return GL_TRUE;
relevant = 0;
for(i = 0; i < 3; ++i) {
GLuint swz = GET_SWZ(reg.Swizzle, i);
if (swz != SWIZZLE_NIL && swz != SWIZZLE_ZERO)
relevant |= 1 << i;
}
if ((reg.NegateBase & relevant) && ((reg.NegateBase & relevant) != relevant))
return GL_FALSE;
return GL_TRUE;
}
}
/**
* Implement a MOV with a potentially non-native swizzle.
*
* The only thing we *cannot* do in an ALU instruction is per-component
* negation. Therefore, we split the MOV into two instructions when necessary.
*/
static void nqssadce_build_swizzle(struct nqssadce_state *s,
struct prog_dst_register dst, struct prog_src_register src)
{
struct prog_instruction *inst;
GLuint negatebase[2] = { 0, 0 };
int i;
for(i = 0; i < 4; ++i) {
GLuint swz = GET_SWZ(src.Swizzle, i);
if (swz == SWIZZLE_NIL)
continue;
negatebase[GET_BIT(src.NegateBase, i)] |= 1 << i;
}
_mesa_insert_instructions(s->Program, s->IP, (negatebase[0] ? 1 : 0) + (negatebase[1] ? 1 : 0));
inst = s->Program->Instructions + s->IP;
for(i = 0; i <= 1; ++i) {
if (!negatebase[i])
continue;
inst->Opcode = OPCODE_MOV;
inst->DstReg = dst;
inst->DstReg.WriteMask = negatebase[i];
inst->SrcReg[0] = src;
inst++;
s->IP++;
}
}
static GLuint build_dtm(GLuint depthmode)
{
switch(depthmode) {
default:
case GL_LUMINANCE: return 0;
case GL_INTENSITY: return 1;
case GL_ALPHA: return 2;
}
}
static GLuint build_func(GLuint comparefunc)
{
return comparefunc - GL_NEVER;
}
/**
* Collect all external state that is relevant for compiling the given
* fragment program.
*/
static void build_state(
r600ContextPtr r600,
struct r500_fragment_program *fp,
struct r500_fragment_program_external_state *state)
{
int unit;
_mesa_bzero(state, sizeof(*state));
for(unit = 0; unit < 16; ++unit) {
if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) {
struct gl_texture_object* tex = r600->radeon.glCtx->Texture.Unit[unit]._Current;
state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode);
state->unit[unit].texture_compare_func = build_func(tex->CompareFunc);
}
}
}
static void dump_program(struct r500_fragment_program_code *code);
void r500TranslateFragmentShader(r600ContextPtr r600,
struct r500_fragment_program *fp)
{
struct r500_fragment_program_external_state state;
build_state(r600, fp, &state);
if (_mesa_memcmp(&fp->state, &state, sizeof(state))) {
/* TODO: cache compiled programs */
fp->translated = GL_FALSE;
_mesa_memcpy(&fp->state, &state, sizeof(state));
}
if (!fp->translated) {
struct r500_fragment_program_compiler compiler;
compiler.r600 = r600;
compiler.fp = fp;
compiler.code = &fp->code;
compiler.program = _mesa_clone_program(r600->radeon.glCtx, &fp->mesa_program.Base);
if (RADEON_DEBUG & DEBUG_PIXEL) {
_mesa_printf("Compiler: Initial program:\n");
_mesa_print_program(compiler.program);
}
insert_WPOS_trailer(&compiler);
struct radeon_program_transformation transformations[] = {
{ &transform_TEX, &compiler },
{ &radeonTransformALU, 0 },
{ &radeonTransformDeriv, 0 },
{ &radeonTransformTrigScale, 0 }
};
radeonLocalTransform(r600->radeon.glCtx, compiler.program,
4, transformations);
if (RADEON_DEBUG & DEBUG_PIXEL) {
_mesa_printf("Compiler: after native rewrite:\n");
_mesa_print_program(compiler.program);
}
struct radeon_nqssadce_descr nqssadce = {
.Init = &nqssadce_init,
.IsNativeSwizzle = &is_native_swizzle,
.BuildSwizzle = &nqssadce_build_swizzle,
.RewriteDepthOut = GL_TRUE
};
radeonNqssaDce(r600->radeon.glCtx, compiler.program, &nqssadce);
if (RADEON_DEBUG & DEBUG_PIXEL) {
_mesa_printf("Compiler: after NqSSA-DCE:\n");
_mesa_print_program(compiler.program);
}
fp->translated = r500FragmentProgramEmit(&compiler);
/* Subtle: Rescue any parameters that have been added during transformations */
_mesa_free_parameter_list(fp->mesa_program.Base.Parameters);
fp->mesa_program.Base.Parameters = compiler.program->Parameters;
compiler.program->Parameters = 0;
_mesa_reference_program(r600->radeon.glCtx, &compiler.program, 0);
r600UpdateStateParameters(r600->radeon.glCtx, _NEW_PROGRAM);
if (RADEON_DEBUG & DEBUG_PIXEL) {
if (fp->translated) {
_mesa_printf("Machine-readable code:\n");
dump_program(&fp->code);
}
}
}
update_params(r600, fp);
}
static char *toswiz(int swiz_val) {
switch(swiz_val) {
case 0: return "R";
case 1: return "G";
case 2: return "B";
case 3: return "A";
case 4: return "0";
case 5: return "1/2";
case 6: return "1";
case 7: return "U";
}
return NULL;
}
static char *toop(int op_val)
{
char *str = NULL;
switch (op_val) {
case 0: str = "MAD"; break;
case 1: str = "DP3"; break;
case 2: str = "DP4"; break;
case 3: str = "D2A"; break;
case 4: str = "MIN"; break;
case 5: str = "MAX"; break;
case 6: str = "Reserved"; break;
case 7: str = "CND"; break;
case 8: str = "CMP"; break;
case 9: str = "FRC"; break;
case 10: str = "SOP"; break;
case 11: str = "MDH"; break;
case 12: str = "MDV"; break;
}
return str;
}
static char *to_alpha_op(int op_val)
{
char *str = NULL;
switch (op_val) {
case 0: str = "MAD"; break;
case 1: str = "DP"; break;
case 2: str = "MIN"; break;
case 3: str = "MAX"; break;
case 4: str = "Reserved"; break;
case 5: str = "CND"; break;
case 6: str = "CMP"; break;
case 7: str = "FRC"; break;
case 8: str = "EX2"; break;
case 9: str = "LN2"; break;
case 10: str = "RCP"; break;
case 11: str = "RSQ"; break;
case 12: str = "SIN"; break;
case 13: str = "COS"; break;
case 14: str = "MDH"; break;
case 15: str = "MDV"; break;
}
return str;
}
static char *to_mask(int val)
{
char *str = NULL;
switch(val) {
case 0: str = "NONE"; break;
case 1: str = "R"; break;
case 2: str = "G"; break;
case 3: str = "RG"; break;
case 4: str = "B"; break;
case 5: str = "RB"; break;
case 6: str = "GB"; break;
case 7: str = "RGB"; break;
case 8: str = "A"; break;
case 9: str = "AR"; break;
case 10: str = "AG"; break;
case 11: str = "ARG"; break;
case 12: str = "AB"; break;
case 13: str = "ARB"; break;
case 14: str = "AGB"; break;
case 15: str = "ARGB"; break;
}
return str;
}
static char *to_texop(int val)
{
switch(val) {
case 0: return "NOP";
case 1: return "LD";
case 2: return "TEXKILL";
case 3: return "PROJ";
case 4: return "LODBIAS";
case 5: return "LOD";
case 6: return "DXDY";
}
return NULL;
}
static void dump_program(struct r500_fragment_program_code *code)
{
fprintf(stderr, "R500 Fragment Program:\n--------\n");
int n;
uint32_t inst;
uint32_t inst0;
char *str = NULL;
if (code->const_nr) {
fprintf(stderr, "--------\nConstants:\n");
for (n = 0; n < code->const_nr; n++) {
fprintf(stderr, "Constant %d: %i[%i]\n", n,
code->constant[n].File, code->constant[n].Index);
}
fprintf(stderr, "--------\n");
}
for (n = 0; n < code->inst_end+1; n++) {
inst0 = inst = code->inst[n].inst0;
fprintf(stderr,"%d\t0:CMN_INST 0x%08x:", n, inst);
switch(inst & 0x3) {
case R500_INST_TYPE_ALU: str = "ALU"; break;
case R500_INST_TYPE_OUT: str = "OUT"; break;
case R500_INST_TYPE_FC: str = "FC"; break;
case R500_INST_TYPE_TEX: str = "TEX"; break;
};
fprintf(stderr,"%s %s %s %s %s ", str,
inst & R500_INST_TEX_SEM_WAIT ? "TEX_WAIT" : "",
inst & R500_INST_LAST ? "LAST" : "",
inst & R500_INST_NOP ? "NOP" : "",
inst & R500_INST_ALU_WAIT ? "ALU WAIT" : "");
fprintf(stderr,"wmask: %s omask: %s\n", to_mask((inst >> 11) & 0xf),
to_mask((inst >> 15) & 0xf));
switch(inst0 & 0x3) {
case 0:
case 1:
fprintf(stderr,"\t1:RGB_ADDR 0x%08x:", code->inst[n].inst1);
inst = code->inst[n].inst1;
fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
inst & 0xff, (inst & (1<<8)) ? 'c' : 't',
(inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't',
(inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't',
(inst >> 30));
fprintf(stderr,"\t2:ALPHA_ADDR 0x%08x:", code->inst[n].inst2);
inst = code->inst[n].inst2;
fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
inst & 0xff, (inst & (1<<8)) ? 'c' : 't',
(inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't',
(inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't',
(inst >> 30));
fprintf(stderr,"\t3 RGB_INST: 0x%08x:", code->inst[n].inst3);
inst = code->inst[n].inst3;
fprintf(stderr,"rgb_A_src:%d %s/%s/%s %d rgb_B_src:%d %s/%s/%s %d\n",
(inst) & 0x3, toswiz((inst >> 2) & 0x7), toswiz((inst >> 5) & 0x7), toswiz((inst >> 8) & 0x7),
(inst >> 11) & 0x3,
(inst >> 13) & 0x3, toswiz((inst >> 15) & 0x7), toswiz((inst >> 18) & 0x7), toswiz((inst >> 21) & 0x7),
(inst >> 24) & 0x3);
fprintf(stderr,"\t4 ALPHA_INST:0x%08x:", code->inst[n].inst4);
inst = code->inst[n].inst4;
fprintf(stderr,"%s dest:%d%s alp_A_src:%d %s %d alp_B_src:%d %s %d w:%d\n", to_alpha_op(inst & 0xf),
(inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"",
(inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), (inst >> 17) & 0x3,
(inst >> 19) & 0x3, toswiz((inst >> 21) & 0x7), (inst >> 24) & 0x3,
(inst >> 31) & 0x1);
fprintf(stderr,"\t5 RGBA_INST: 0x%08x:", code->inst[n].inst5);
inst = code->inst[n].inst5;
fprintf(stderr,"%s dest:%d%s rgb_C_src:%d %s/%s/%s %d alp_C_src:%d %s %d\n", toop(inst & 0xf),
(inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"",
(inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), toswiz((inst >> 17) & 0x7), toswiz((inst >> 20) & 0x7),
(inst >> 23) & 0x3,
(inst >> 25) & 0x3, toswiz((inst >> 27) & 0x7), (inst >> 30) & 0x3);
break;
case 2:
break;
case 3:
inst = code->inst[n].inst1;
fprintf(stderr,"\t1:TEX_INST: 0x%08x: id: %d op:%s, %s, %s %s\n", inst, (inst >> 16) & 0xf,
to_texop((inst >> 22) & 0x7), (inst & (1<<25)) ? "ACQ" : "",
(inst & (1<<26)) ? "IGNUNC" : "", (inst & (1<<27)) ? "UNSCALED" : "SCALED");
inst = code->inst[n].inst2;
fprintf(stderr,"\t2:TEX_ADDR: 0x%08x: src: %d%s %s/%s/%s/%s dst: %d%s %s/%s/%s/%s\n", inst,
inst & 127, inst & (1<<7) ? "(rel)" : "",
toswiz((inst >> 8) & 0x3), toswiz((inst >> 10) & 0x3),
toswiz((inst >> 12) & 0x3), toswiz((inst >> 14) & 0x3),
(inst >> 16) & 127, inst & (1<<23) ? "(rel)" : "",
toswiz((inst >> 24) & 0x3), toswiz((inst >> 26) & 0x3),
toswiz((inst >> 28) & 0x3), toswiz((inst >> 30) & 0x3));
fprintf(stderr,"\t3:TEX_DXDY: 0x%08x\n", code->inst[n].inst3);
break;
}
fprintf(stderr,"\n");
}
}
src/mesa/drivers/dri/r600/r700_fragprog_emit.c
-327
View File
@@ -1,327 +0,0 @@
/*
* Copyright (C) 2005 Ben Skeggs.
*
* Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
* Adaptation and modification for ATI/AMD Radeon R500 GPU chipsets.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
/**
* \file
*
* \author Ben Skeggs <darktama@iinet.net.au>
*
* \author Jerome Glisse <j.glisse@gmail.com>
*
* \author Corbin Simpson <MostAwesomeDude@gmail.com>
*
* \todo Depth write, WPOS/FOGC inputs
*
* \todo FogOption
*
*/
#include "r700_fragprog.h"
#include "radeon_program_pair.h"
#define PROG_CODE \
struct r500_fragment_program_compiler *c = (struct r500_fragment_program_compiler*)data; \
struct r500_fragment_program_code *code = c->code
#define error(fmt, args...) do { \
fprintf(stderr, "%s::%s(): " fmt "\n", \
__FILE__, __FUNCTION__, ##args); \
} while(0)
/**
* Callback to register hardware constants.
*/
static GLboolean emit_const(void *data, GLuint file, GLuint idx, GLuint *hwindex)
{
PROG_CODE;
for (*hwindex = 0; *hwindex < code->const_nr; ++*hwindex) {
if (code->constant[*hwindex].File == file &&
code->constant[*hwindex].Index == idx)
break;
}
if (*hwindex >= code->const_nr) {
if (*hwindex >= PFS_NUM_CONST_REGS) {
error("Out of hw constants!\n");
return GL_FALSE;
}
code->const_nr++;
code->constant[*hwindex].File = file;
code->constant[*hwindex].Index = idx;
}
return GL_TRUE;
}
static GLuint translate_rgb_op(GLuint opcode)
{
switch(opcode) {
case OPCODE_CMP: return R500_ALU_RGBA_OP_CMP;
case OPCODE_DDX: return R500_ALU_RGBA_OP_MDH;
case OPCODE_DDY: return R500_ALU_RGBA_OP_MDV;
case OPCODE_DP3: return R500_ALU_RGBA_OP_DP3;
case OPCODE_DP4: return R500_ALU_RGBA_OP_DP4;
case OPCODE_FRC: return R500_ALU_RGBA_OP_FRC;
default:
error("translate_rgb_op(%d): unknown opcode\n", opcode);
/* fall through */
case OPCODE_NOP:
/* fall through */
case OPCODE_MAD: return R500_ALU_RGBA_OP_MAD;
case OPCODE_MAX: return R500_ALU_RGBA_OP_MAX;
case OPCODE_MIN: return R500_ALU_RGBA_OP_MIN;
case OPCODE_REPL_ALPHA: return R500_ALU_RGBA_OP_SOP;
}
}
static GLuint translate_alpha_op(GLuint opcode)
{
switch(opcode) {
case OPCODE_CMP: return R500_ALPHA_OP_CMP;
case OPCODE_COS: return R500_ALPHA_OP_COS;
case OPCODE_DDX: return R500_ALPHA_OP_MDH;
case OPCODE_DDY: return R500_ALPHA_OP_MDV;
case OPCODE_DP3: return R500_ALPHA_OP_DP;
case OPCODE_DP4: return R500_ALPHA_OP_DP;
case OPCODE_EX2: return R500_ALPHA_OP_EX2;
case OPCODE_FRC: return R500_ALPHA_OP_FRC;
case OPCODE_LG2: return R500_ALPHA_OP_LN2;
default:
error("translate_alpha_op(%d): unknown opcode\n", opcode);
/* fall through */
case OPCODE_NOP:
/* fall through */
case OPCODE_MAD: return R500_ALPHA_OP_MAD;
case OPCODE_MAX: return R500_ALPHA_OP_MAX;
case OPCODE_MIN: return R500_ALPHA_OP_MIN;
case OPCODE_RCP: return R500_ALPHA_OP_RCP;
case OPCODE_RSQ: return R500_ALPHA_OP_RSQ;
case OPCODE_SIN: return R500_ALPHA_OP_SIN;
}
}
static GLuint fix_hw_swizzle(GLuint swz)
{
if (swz == 5) swz = 6;
if (swz == SWIZZLE_NIL) swz = 4;
return swz;
}
static GLuint translate_arg_rgb(struct radeon_pair_instruction *inst, int arg)
{
GLuint t = inst->RGB.Arg[arg].Source;
int comp;
t |= inst->RGB.Arg[arg].Negate << 11;
t |= inst->RGB.Arg[arg].Abs << 12;
for(comp = 0; comp < 3; ++comp)
t |= fix_hw_swizzle(GET_SWZ(inst->RGB.Arg[arg].Swizzle, comp)) << (3*comp + 2);
return t;
}
static GLuint translate_arg_alpha(struct radeon_pair_instruction *inst, int i)
{
GLuint t = inst->Alpha.Arg[i].Source;
t |= fix_hw_swizzle(inst->Alpha.Arg[i].Swizzle) << 2;
t |= inst->Alpha.Arg[i].Negate << 5;
t |= inst->Alpha.Arg[i].Abs << 6;
return t;
}
static void use_temporary(struct r500_fragment_program_code* code, GLuint index)
{
if (index > code->max_temp_idx)
code->max_temp_idx = index;
}
static GLuint use_source(struct r500_fragment_program_code* code, struct radeon_pair_instruction_source src)
{
if (!src.Constant)
use_temporary(code, src.Index);
return src.Index | src.Constant << 8;
}
/**
* Emit a paired ALU instruction.
*/
static GLboolean emit_paired(void *data, struct radeon_pair_instruction *inst)
{
PROG_CODE;
if (code->inst_end >= 511) {
error("emit_alu: Too many instructions");
return GL_FALSE;
}
int ip = ++code->inst_end;
code->inst[ip].inst5 = translate_rgb_op(inst->RGB.Opcode);
code->inst[ip].inst4 = translate_alpha_op(inst->Alpha.Opcode);
if (inst->RGB.OutputWriteMask || inst->Alpha.OutputWriteMask || inst->Alpha.DepthWriteMask)
code->inst[ip].inst0 = R500_INST_TYPE_OUT;
else
code->inst[ip].inst0 = R500_INST_TYPE_ALU;
code->inst[ip].inst0 |= R500_INST_TEX_SEM_WAIT;
code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11) | (inst->Alpha.WriteMask << 14);
code->inst[ip].inst0 |= (inst->RGB.OutputWriteMask << 15) | (inst->Alpha.OutputWriteMask << 18);
if (inst->Alpha.DepthWriteMask) {
code->inst[ip].inst4 |= R500_ALPHA_W_OMASK;
c->fp->writes_depth = GL_TRUE;
}
code->inst[ip].inst4 |= R500_ALPHA_ADDRD(inst->Alpha.DestIndex);
code->inst[ip].inst5 |= R500_ALU_RGBA_ADDRD(inst->RGB.DestIndex);
use_temporary(code, inst->Alpha.DestIndex);
use_temporary(code, inst->RGB.DestIndex);
if (inst->RGB.Saturate)
code->inst[ip].inst0 |= R500_INST_RGB_CLAMP;
if (inst->Alpha.Saturate)
code->inst[ip].inst0 |= R500_INST_ALPHA_CLAMP;
code->inst[ip].inst1 |= R500_RGB_ADDR0(use_source(code, inst->RGB.Src[0]));
code->inst[ip].inst1 |= R500_RGB_ADDR1(use_source(code, inst->RGB.Src[1]));
code->inst[ip].inst1 |= R500_RGB_ADDR2(use_source(code, inst->RGB.Src[2]));
code->inst[ip].inst2 |= R500_ALPHA_ADDR0(use_source(code, inst->Alpha.Src[0]));
code->inst[ip].inst2 |= R500_ALPHA_ADDR1(use_source(code, inst->Alpha.Src[1]));
code->inst[ip].inst2 |= R500_ALPHA_ADDR2(use_source(code, inst->Alpha.Src[2]));
code->inst[ip].inst3 |= translate_arg_rgb(inst, 0) << R500_ALU_RGB_SEL_A_SHIFT;
code->inst[ip].inst3 |= translate_arg_rgb(inst, 1) << R500_ALU_RGB_SEL_B_SHIFT;
code->inst[ip].inst5 |= translate_arg_rgb(inst, 2) << R500_ALU_RGBA_SEL_C_SHIFT;
code->inst[ip].inst4 |= translate_arg_alpha(inst, 0) << R500_ALPHA_SEL_A_SHIFT;
code->inst[ip].inst4 |= translate_arg_alpha(inst, 1) << R500_ALPHA_SEL_B_SHIFT;
code->inst[ip].inst5 |= translate_arg_alpha(inst, 2) << R500_ALU_RGBA_ALPHA_SEL_C_SHIFT;
return GL_TRUE;
}
static GLuint translate_strq_swizzle(struct prog_src_register src)
{
GLuint swiz = 0;
int i;
for (i = 0; i < 4; i++)
swiz |= (GET_SWZ(src.Swizzle, i) & 0x3) << i*2;
return swiz;
}
/**
* Emit a single TEX instruction
*/
static GLboolean emit_tex(void *data, struct prog_instruction *inst)
{
PROG_CODE;
if (code->inst_end >= 511) {
error("emit_tex: Too many instructions");
return GL_FALSE;
}
int ip = ++code->inst_end;
code->inst[ip].inst0 = R500_INST_TYPE_TEX
| (inst->DstReg.WriteMask << 11)
| R500_INST_TEX_SEM_WAIT;
code->inst[ip].inst1 = R500_TEX_ID(inst->TexSrcUnit)
| R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
if (inst->TexSrcTarget == TEXTURE_RECT_INDEX)
code->inst[ip].inst1 |= R500_TEX_UNSCALED;
switch (inst->Opcode) {
case OPCODE_KIL:
code->inst[ip].inst1 |= R500_TEX_INST_TEXKILL;
break;
case OPCODE_TEX:
code->inst[ip].inst1 |= R500_TEX_INST_LD;
break;
case OPCODE_TXB:
code->inst[ip].inst1 |= R500_TEX_INST_LODBIAS;
break;
case OPCODE_TXP:
code->inst[ip].inst1 |= R500_TEX_INST_PROJ;
break;
default:
error("emit_tex can't handle opcode %x\n", inst->Opcode);
}
code->inst[ip].inst2 = R500_TEX_SRC_ADDR(inst->SrcReg[0].Index)
| (translate_strq_swizzle(inst->SrcReg[0]) << 8)
| R500_TEX_DST_ADDR(inst->DstReg.Index)
| R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G
| R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A;
return GL_TRUE;
}
static const struct radeon_pair_handler pair_handler = {
.EmitConst = emit_const,
.EmitPaired = emit_paired,
.EmitTex = emit_tex,
.MaxHwTemps = 128
};
GLboolean r500FragmentProgramEmit(struct r500_fragment_program_compiler *compiler)
{
struct r500_fragment_program_code *code = compiler->code;
_mesa_bzero(code, sizeof(*code));
code->max_temp_idx = 1;
code->inst_offset = 0;
code->inst_end = -1;
if (!radeonPairProgram(compiler->r600->radeon.glCtx, compiler->program, &pair_handler, compiler))
return GL_FALSE;
if ((code->inst[code->inst_end].inst0 & R500_INST_TYPE_MASK) != R500_INST_TYPE_OUT) {
/* This may happen when dead-code elimination is disabled or
* when most of the fragment program logic is leading to a KIL */
if (code->inst_end >= 511) {
error("Introducing fake OUT: Too many instructions");
return GL_FALSE;
}
int ip = ++code->inst_end;
code->inst[ip].inst0 = R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT;
}
return GL_TRUE;
}