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ir3: Use INVALID_REG in array store

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We now use INVALID_REG to mean that a source or destination does not
have a preassigned register. We ignore this for anything but inputs and
outputs for now, but don't make it look like we're preassigning the
array to r0.x. This also will allow us to assert that preassigned
registers are in the correct range.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
This commit is contained in:
Connor Abbott
2023-10-31 18:38:01 +01:00
committed by Marge Bot
parent b2cf2dfd78
commit c00e06bc62
1 changed files with 2 additions and 2 deletions
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4
src/freedreno/ir3/ir3_context.c
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@@ -616,14 +616,14 @@ ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n,
mov->barrier_class = IR3_BARRIER_ARRAY_W;
mov->barrier_conflict = IR3_BARRIER_ARRAY_R | IR3_BARRIER_ARRAY_W;
dst = ir3_dst_create(
mov, 0,
mov, INVALID_REG,
IR3_REG_SSA | IR3_REG_ARRAY | flags | COND(address, IR3_REG_RELATIV));
dst->instr = mov;
dst->size = arr->length;
dst->array.id = arr->id;
dst->array.offset = n;
dst->array.base = INVALID_REG;
ir3_src_create(mov, 0, IR3_REG_SSA | flags)->def = src->dsts[0];
ir3_src_create(mov, INVALID_REG, IR3_REG_SSA | flags)->def = src->dsts[0];
if (arr->last_write && arr->last_write->instr->block == block)
ir3_reg_set_last_array(mov, dst, arr->last_write);