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radeonsi: Implement POLYGON_OFFSET_UNITS_UNSCALED

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Empirical tests show that the polygon offset
behaviour is entirely determined by the content of
the PA_SU_POLY_OFFSET states, and not by the depth buffer
format bound.

PA_SU_POLY_OFFSET seems to directly set the parameters of
the polygon offset formula, and setting 0 for
PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth
bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled
behaviour.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Axel Davy
2016-06-14 22:41:50 +02:00
parent c2b7b48a54
commit be7957b156
2 changed files with 19 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeonsi/si_pipe.c
+1 -1
View File
@@ -357,6 +357,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
return 1;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
@@ -415,7 +416,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_TGSI_VOTE:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
return 0;
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
src/gallium/drivers/radeonsi/si_state.c
+18 -14
View File
@@ -810,20 +810,24 @@ static void *si_create_rs_state(struct pipe_context *ctx,
float offset_scale = state->offset_scale * 16.0f;
uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
switch (i) {
case 0: /* 16-bit zbuffer */
offset_units *= 4.0f;
pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
break;
case 1: /* 24-bit zbuffer */
offset_units *= 2.0f;
pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
break;
case 2: /* 32-bit zbuffer */
offset_units *= 1.0f;
pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
break;
if (!state->offset_units_unscaled) {
switch (i) {
case 0: /* 16-bit zbuffer */
offset_units *= 4.0f;
pa_su_poly_offset_db_fmt_cntl =
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
break;
case 1: /* 24-bit zbuffer */
offset_units *= 2.0f;
pa_su_poly_offset_db_fmt_cntl =
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
break;
case 2: /* 32-bit zbuffer */
offset_units *= 1.0f;
pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
break;
}
}
si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,