radeonsi: update comments about uniform inlining
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26307>
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@@ -2232,22 +2232,22 @@ struct nir_shader *si_get_nir_shader(struct si_shader *shader,
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* - Register usage and code size decrease (obvious)
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* - Eliminated PS system values are disabled by LLVM
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* (FragCoord, FrontFace, barycentrics)
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* - VS/TES/GS outputs feeding PS are eliminated if outputs are undef.
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* The storage for eliminated outputs is also not allocated.
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* - VS/TES/GS param exports are eliminated if they are undef.
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* The param space for eliminated outputs is also not allocated.
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* - VS/TCS/TES/GS/PS input loads are eliminated (VS relies on DCE in LLVM)
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* - TCS output stores are eliminated
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* - Eliminated PS inputs are removed from PS.NUM_INTERP.
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*
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* TODO: These are things the driver ignores in the final shader code
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* and relies on the default shader info.
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* - Other system values are not eliminated
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* - System values in VS, TCS, TES, GS are not eliminated
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* - uses_discard - if it changed to false
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* - writes_memory - if it changed to false
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* - VS->TCS, VS->GS, TES->GS output stores for the former stage are not
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* eliminated
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* - Eliminated VS/TCS/TES outputs are still allocated. (except when feeding PS)
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* GS outputs are eliminated except for the temporary LDS.
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* Clip distances, gl_PointSize, and PS outputs are eliminated based
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* Clip distances, gl_PointSize, gl_Layer and PS outputs are eliminated based
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* on current states, so we don't care about the shader code.
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*
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* TODO: Merged shaders don't inline uniforms for the first stage.
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