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radv: remove old_fence parameter from si_cs_emit_write_event_eop()

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This parameter is actually useless as the immediate value
can always be zero.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2019-01-17 09:33:36 +01:00
parent 698afa177e
commit bd098884f1
4 changed files with 7 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_cmd_buffer.c
+1 -1
View File
@@ -4779,7 +4779,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
cmd_buffer->device->physical_device->rad_info.chip_class,
radv_cmd_buffer_uses_mec(cmd_buffer),
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
EOP_DATA_SEL_VALUE_32BIT, va, value,
cmd_buffer->gfx9_eop_bug_va);
}
src/amd/vulkan/radv_private.h
-1
View File
@@ -1152,7 +1152,6 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
unsigned event, unsigned event_flags,
unsigned data_sel,
uint64_t va,
uint32_t old_fence,
uint32_t new_fence,
uint64_t gfx9_eop_bug_va);
src/amd/vulkan/radv_query.c
+2 -2
View File
@@ -1569,7 +1569,7 @@ static void emit_end_query(struct radv_cmd_buffer *cmd_buffer,
radv_cmd_buffer_uses_mec(cmd_buffer),
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DATA_SEL_VALUE_32BIT,
avail_va, 0, 1,
avail_va, 1,
cmd_buffer->gfx9_eop_bug_va);
break;
case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
@@ -1704,7 +1704,7 @@ void radv_CmdWriteTimestamp(
mec,
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DATA_SEL_TIMESTAMP,
query_va, 0, 0,
query_va, 0,
cmd_buffer->gfx9_eop_bug_va);
break;
}
src/amd/vulkan/si_cmd_buffer.c
+4 -5
View File
@@ -660,7 +660,6 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
unsigned event, unsigned event_flags,
unsigned data_sel,
uint64_t va,
uint32_t old_fence,
uint32_t new_fence,
uint64_t gfx9_eop_bug_va)
{
@@ -707,7 +706,7 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
radeon_emit(cs, op);
radeon_emit(cs, va);
radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
radeon_emit(cs, old_fence); /* immediate data */
radeon_emit(cs, 0); /* immediate data */
radeon_emit(cs, 0); /* unused */
}
@@ -801,7 +800,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
V_028A90_FLUSH_AND_INV_CB_DATA_TS,
0,
EOP_DATA_SEL_DISCARD,
0, 0, 0,
0, 0,
gfx9_eop_bug_va);
}
}
@@ -868,11 +867,11 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
RADV_CMD_FLAG_INV_VMEM_L1);
}
assert(flush_cnt);
uint32_t old_fence = (*flush_cnt)++;
(*flush_cnt)++;
si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
EOP_DATA_SEL_VALUE_32BIT,
flush_va, old_fence, *flush_cnt,
flush_va, *flush_cnt,
gfx9_eop_bug_va);
radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
*flush_cnt, 0xffffffff);