freedreno/ir3: optimize sam.s2en to sam
Detect when sampler/texture idx are immediate and switch to non s2en encoding. Signed-off-by: Rob Clark <robdclark@gmail.com>
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@@ -29,12 +29,13 @@
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#include "ir3_compiler.h"
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static const struct debug_named_value shader_debug_options[] = {
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{"vs", IR3_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
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{"fs", IR3_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
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{"cs", IR3_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
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{"disasm", IR3_DBG_DISASM, "Dump NIR and adreno shader disassembly"},
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{"optmsgs", IR3_DBG_OPTMSGS,"Enable optimizer debug messages"},
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DEBUG_NAMED_VALUE_END
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{"vs", IR3_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
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{"fs", IR3_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
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{"cs", IR3_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
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{"disasm", IR3_DBG_DISASM, "Dump NIR and adreno shader disassembly"},
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{"optmsgs", IR3_DBG_OPTMSGS, "Enable optimizer debug messages"},
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{"forces2en", IR3_DBG_FORCES2EN, "Force s2en mode for tex sampler instructions"},
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DEBUG_NAMED_VALUE_END
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};
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DEBUG_GET_ONCE_FLAGS_OPTION(ir3_shader_debug, "IR3_SHADER_DEBUG", shader_debug_options, 0)
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@@ -76,6 +76,7 @@ enum ir3_shader_debug {
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IR3_DBG_SHADER_CS = 0x04,
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IR3_DBG_DISASM = 0x08,
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IR3_DBG_OPTMSGS = 0x10,
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IR3_DBG_FORCES2EN = 0x20,
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};
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extern enum ir3_shader_debug ir3_shader_debug;
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@@ -613,6 +613,34 @@ instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
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break;
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}
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}
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/* Handle converting a sam.s2en (taking samp/tex idx params via
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* register) into a normal sam (encoding immediate samp/tex idx)
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* if they are immediate. This saves some instructions and regs
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* in the common case where we know samp/tex at compile time:
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*/
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if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
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!(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
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/* The first src will be a fan-in (collect), if both of it's
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* two sources are mov from imm, then we can
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*/
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struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
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debug_assert(samp_tex->opc == OPC_META_FI);
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struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
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struct ir3_instruction *tex = ssa(samp_tex->regs[2]);
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if ((samp->opc == OPC_MOV) &&
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(samp->regs[1]->flags & IR3_REG_IMMED) &&
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(tex->opc == OPC_MOV) &&
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(tex->regs[1]->flags & IR3_REG_IMMED)) {
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instr->flags &= ~IR3_INSTR_S2EN;
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instr->cat5.samp = samp->regs[1]->iim_val;
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instr->cat5.tex = tex->regs[1]->iim_val;
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instr->regs[1]->instr = NULL;
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}
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}
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}
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void
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