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radv: Fix barriers with cp dma

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We need to wait for cp dma if VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT or
VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT are set.

Closes: #5911
Fixes: 4b9bc4791b ("radv: only sync CP DMA for transfer operations or bottom pipe")

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15933>
This commit is contained in:
Konstantin Seurer
2022-04-13 21:02:55 +02:00
committed by Marge Bot
parent d703a0e808
commit bbdf22ce13
1 changed files with 4 additions and 3 deletions
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src/amd/vulkan/radv_cmd_buffer.c
+4 -3
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@@ -8452,9 +8452,10 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfo *dep_inf
/* Make sure CP DMA is idle because the driver might have performed a DMA operation for copying a
* buffer (or a MSAA image using FMASK) or updated a buffer which is a transfer operation.
*/
if (src_stage_mask & (VK_PIPELINE_STAGE_2_COPY_BIT |
VK_PIPELINE_STAGE_2_TRANSFER_BIT |
VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT))
if (src_stage_mask &
(VK_PIPELINE_STAGE_2_COPY_BIT | VK_PIPELINE_STAGE_2_CLEAR_BIT |
VK_PIPELINE_STAGE_2_TRANSFER_BIT | VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT |
VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT))
si_cp_dma_wait_for_idle(cmd_buffer);
cmd_buffer->state.flush_bits |= dst_flush_bits;