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i965: Use helper function intel_get_tile_dims() in surface setup

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It takes care of using the correct tile width if we later use other
tiling patterns for aux miptree.

V2: Remove the comment about using Yf for aux miptree.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
This commit is contained in:
Anuj Phogat
2015-07-09 10:47:17 -07:00
parent 1dc41be9eb
commit bbbc9fd8e5
1 changed files with 12 additions and 2 deletions
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src/mesa/drivers/dri/i965/gen8_surface_state.c
+12 -2
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@@ -276,8 +276,13 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
}
if (aux_mt) {
uint32_t tile_w, tile_h;
assert(aux_mt->tiling == I915_TILING_Y);
intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode,
aux_mt->cpp, &tile_w, &tile_h);
surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
SET_FIELD((aux_mt->pitch / tile_w) - 1,
GEN8_SURFACE_AUX_PITCH) |
aux_mode;
} else {
surf[6] = 0;
@@ -501,8 +506,13 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
}
if (aux_mt) {
uint32_t tile_w, tile_h;
assert(aux_mt->tiling == I915_TILING_Y);
intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode,
aux_mt->cpp, &tile_w, &tile_h);
surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
SET_FIELD((aux_mt->pitch / tile_w) - 1,
GEN8_SURFACE_AUX_PITCH) |
aux_mode;
} else {
surf[6] = 0;